This paper describes millimeter-wave (MMW) system technologies for wireless communications, imaging, and sensing. MMW systems have advantages of large bandwidth and short wavelength, and recent progress in electronic and photonic device enables us to handle MMW signals easily at low cost. State-of-the-art MMW wireless communications systems can transmit over-10-Gbit/s data, and research on transmission characteristics is progressing steadily. MMW imaging systems using near-field dispersion can achieve high resolution, and they are starting to be used for non-destructive inspections of infrastructure. An MMW sensing system based on photonic technologies enable us to cover large bandwidths and is now being investigated for remote sensing of gasses in the fields of radio astronomy and disaster prevention.

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This paper describes photonic technologies for millimeter-wave generation and distribution. External modulation would be useful for stable and high-quality radio-over-fiber signal generation, where frequency stability and spurious suppression are very important for radio services such as mobile communications, radio locations etc. This paper provides outline of radio-over-fiber signal generation techniques. Precise and high-speed lightwave optical modulation would play important roles for suppression of undesired spectrum components. Photonic harmonic generation would be useful for very high-frequency signals. Reciprocating optical modulators consisting of optical modulators and fiber Bragg gratings can provide optical modulation by sub-THz signals.

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This paper reviews two important candidates of millimeter- and sub-millimeter-wave applications, InP- and GaN-based high electron mobility transistors (HEMTs). For both devices, the gate length scaling has already well developed to the dimension of 15–30 nm. For further improvement in the cutoff frequency, an importance of the careful managements of parasitic components in the devices is discussed. Successful reduction of the parasitic gate delay time will enable us to achieve a cutoff frequency of over 1 THz in InP-based HEMTs and that of over 500 GHz in GaN-based HEMTs.

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Recent progress and prospects of terahertz CMOS integrated circuits is reviewed. The development of terahertz CMOS is somewhat different from the conventional digital and RF CMOS evolution, in that it is not fueled as much by technology scaling. Rather, the key enablers are progress in high-frequency device characterization and modeling techniques and also in design techniques near transistor’s active operation limit, f_max.

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To increase the output voltage range efficiently in distributed generation system, a novel high step-up and low switches voltage stress boost converter with charge pump capacitor is proposed in this paper. The structure and basic operating principles analysis are provided, but also the results of the analysis are verified by simulation and experiment.

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In SSD-based All Flash Array (AFA), Redundant Array of Independent Disks (RAID) technologies are widely used to cope with drive failures and sector errors. However, the redundancy in disk level is either insufficient like RAID-5 or excessive like RAID-6. In order to combat the two types of errors, we combine the RAID-5 scheme with a Flash-aware Intra-disk Redundancy (FAIDR) scheme. For saving parity space, the ratio of redundancy in the FAIDR scheme grows with the increasing of sector errors. However, the parity handling overhead is significant. As NAND Flash blocks can’t be updated before erase, we establish all FAIDR stripes on the physical page number of blocks regardless of the page state. Thus, the parity update operations in FAIDR are eliminated. Simulation results show that the proposed scheme has the ability to ensure the AFA’s reliability in its all lifetime. It gains 41 percent storage capacity in comparison to RAID-6. And it only leads to very small performance loss compared with pure RAID-5.

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This paper presents an efficient multi-standard decoder for quasi-cyclic low-density parity-check (QC-LDPC) codes. By employing the configurable multi-bank memory structure, simplified permutation network and multiple pipelined datapaths, the decoder can efficiently support WiMAX and WiFi standards without any structural changes. The offset-min-sum-based row-layered decoding algorithm is adopted to reduce the computation complexity. Based on these optimizations, the proposed decoder can achieve about 658 Mbps (1410 Mbps) and 527 Mbps (1129 Mbps) for WiMAX and WiFi standards on TSMC 130 nm (and 65 nm) Application Specific Integrated Circuits (ASICs) platforms, respectively. Compared with the previous works, the throughput can obtain up to 10× improvement for WiMAX standard and 5× improvement for WiFi standard.

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A compensation technique for time alignment of envelope and phase paths in an envelope delta-sigma modulator (EDSM) is proposed. In this technique, two controllable delays are intentionally added, and a combination of the two delays compensates a time misalignment caused by the inherent processing delay of a delta-sigma modulator (DSM) and the difference of propagation delays on the asymmetric envelope and phase paths. One of the two delays is a digital sample delay, which is added in the digital domain before a digital-to-analog converter (DAC). The other delay is obtained by the use of D flip flops (DFFs) followed by a DSM, which is possible because the output of a DSM is changed by a clock. The validity of the proposed technique is confirmed by simulation.

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Often, the demand for optimal and harmonious operation of multi-motor control systems requires sharing of feedback information from one drive to other drives. From the point of view of controller implementation, a multi-controller structure degrades the system integration and requires data communication among chips. The aim of this paper is to propose a fully integrated single chip solution for a cross-coupling multi-motor control system. The proposed speed controller with time-division multiplexing scheme can simplify the entire system, making possible the implementation on a single device. The experimental results confirm the implementation feasibility and the effectiveness of the proposed single chip system.

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This letter proposes an efficient hardware accelerator of one-dimensional (1D) eight-point Loeffler discrete cosine transform (DCT) for small portable devices. For continuous 1D input data streams, the accelerator uses only 13 adders and can calculate one DCT coefficient per clock cycle, which is the optimal throughput for the considered applications. Implementation results show that the accelerator can support real-time encoding of practical video sequences and can be a good alternative for small portable applications.

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A novel bandwidth enhancement technique based on a modified regulated cascode (RGC) transimpedance amplifier (TIA) is proposed and realized. The post stage of the TIA adopts capacitive degeneration and π-type peaking network, maintaining the wideband and low group delay characteristics without increasing power dissipation. The TIA is implemented in a 0.18 µm SiGe BiCMOS technology and tested with an on-chip 300 fF capacitor to emulate a photodiode. The measured transimpedance gain is 61 dBΩ with a −3 dB bandwidth of 15 GHz. The chip consumes 32 mW power from a single 3.3 V supply and occupies the area of only 0.3 mm².

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In this paper, a novel low-energy capacitor switching scheme for low power successive approximation register (SAR) analog to digital converter (ADC) is presented. The proposed scheme in this paper can achieve 99.9% savings in switching energy and 75% less number of capacitors compared to the conventional architecture. The proposed method is the most energy-efficient switching scheme among the reported switching techniques.

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A 65–77 GHz low power, meander-type transmission line CMOS low-noise amplifier for E-band millimetre-wave communication using 90 nm MS/RF CMOS process is demonstrated. The low-noise amplifier consists of multi-stage cascaded common-source amplifiers with optimized noise figure, power gain, and power consumption. The LNA achieves 11.7 dB power gain, 5.5 dB noise figure, and 17.7 mW power consumption. The meander-type transmission line circuit design is adopted to reduce chip area; the total transmission line area in LNA is only 0.024 mm².

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Resistorless dual-mode electronically tunable quadrature oscillator using a single current controlled current conveyor transconductance amplifier (CCCCTA) and two grounded capacitors is presented. The proposed circuit can provide both voltage-mode and current-mode simultaneously. The circuit with grounded capacitors enjoys resistorless, electronically tunable, non-interactive frequency and condition control, generates two quadrature current outputs at high impedance nodes and two quadrature voltage outputs. H-Simulation program with integrated circuit emphasis (H-Spice) simulations using Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 µm complementary metal oxide semiconductor (CMOS) technology process parameters are given to validate theoretical predictions.

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Bit error rates (BERs) of all-optical flip-flop operations with AND-gate functionality using a 1.55-µm polarization bistable vertical-cavity surface-emitting laser (VCSEL) were measured. Optical data pulses of a 500-Mb/s return-to-zero pseudo-random bit-sequence were used. The best BER we obtained was 5.00 × 10⁻⁹ and the eye diagram was clearly open. Input-pulse power was about 17 dB lower than VCSEL output power. From the BER variation for the set-pulse power under fixed data-pulse power, we found that fluctuations in the switching threshold and power of AND pulse (combination of data and set pulses) affect the BER. We also evaluated the BER of memory operations.

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In this paper, a tunable dual-band bandpass filter using asymmetrical varactor-loaded half-wavelength resonators (HWR) and defected ground structure (DGS) is proposed. First, varactors are added at the end of the conventional HWRs to change their resonant frequencies. And to determine the bandwidth of the passbands, the coupling coefficients are calculated to the requirements based on the theoretical analyses. However, the isolation will deteriorate if the passbands are tuned close to each other. Then in order to solve this problem, a pair of circular DGS is introduced at the ground plane of the filter. This structure can prevent electromagnetic energy from propagating at some certain frequency point and if it is designed between the passbands, the isolation will be improved. In our design, the proposed dual-band bandpass filter using varactor-loaded HWRs and DGS is simulated and fabricated. The simulated results and measured results are in good agreement and the proposed filter can be applied in microwave circuits and communication systems.

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