Video artificial intelligence (AI) applications for edges/terminals, such as non-visual drone flight, require object detection in high-definition video in order to detect a wide range of objects with one camera at once. To enable satisfying this requirement, we propose a new high-definition object detection technology based on an AI inference scheme and its implementation. In the technology, multiple object detectors cooperate to detect small and large objects in high-definition video. The evaluation results show that our technology can achieve 2.1 times higher detection performance in full HD images thanks to the cooperation of three object detectors.

A hybrid cache architecture (HCA) is introduced to alleviate the drawbacks of non-volatile memory (NVM) technologies. Although researchers have offered meaningful ways to conserve energy, little attention has been paid to focus on write counts that are non-uniformly spread over a cache line. We propose a novel HCA to reduce the NVM write counts by exploiting bit-level write patterns. The data array is refined to separately store bits in the cache line to the NVM region and the SRAM region. As a result, 20.1% of energy is saved over prior works.

A 54-GHz two-stage pseudo-differential common source power amplifier (PA) is implemented using dual-gated transistors (DGT). DGT structure is able to enhance both the linearity and back-off efficiency without consuming extra dc power. The nonlinear characteristics of the transistor can be compensated by adjusting the gate width and overdrive voltage of each transistor in the DGT. Besides, the dc power consumption of the DGT amplifier scales with the amplitude of the input signal, resulting in enhanced PAE at back-off. Fabricated in a 65-nm CMOS process, the measured small-signal gain of the 0.5 × 0.98mm² PA is 17dB at 52GHz while consuming 24mW from a 1-V supply. The maximum saturated output power is 10.5dBm with a peak PAE of 23.3% measured at 54GHz; the measured output power and PAE at 1-dB compression is 7.6dBm and 17%, respectively.

This paper proposes a direct 12V-to-1V hybrid converter using a switched-capacitor-assisted (SCA) topology, featuring dual-path output current conduction to lower the inductor current. In contrast to the existing dual-path structures, the proposed topology realizes a high step-down conversion with efficiency improvement in heavy-load conditions. Besides, the converter further achieves an efficiency boost in light-load conditions using zero-voltage switching. Designed in a 180-nm SOI BCD process, the proposed converter regulates an output of 0.7∼1.3V from a 12-V input with a peak efficiency of 92%. Under a loading current of 2A, it attains an efficiency over 84% at the 1-V output. Compared with the conventional buck, it achieves an improvement of 9.8% in peak efficiency and 13.6% in maximum-loading efficiency.

This work proposes a hybrid DC-DC converter using a multi-path switched-capacitor-inductor (MPSCI) topology. Assisted by switched-capacitor branches, it features voltage-conversion range extension and inductor power loss reduction, and hence improving the conversion efficiency. Implemented in a 180-nm CMOS process, the proposed converter can regulate an output voltage of 1.8∼3.3V from a 5-V input bus voltage using a 4.7μH inductor (DCR =240mΩ) at a switching frequency of 800kHz. It achieves a peak conversion efficiency of 93.7% when delivering an output current of 1A. Under a maximum loading of 3A, this design still attains an efficiency of up to 85.8%. Furthermore, in contrast to the existing dual-path and conventional buck topologies, the proposed converter realizes an inductor loss reduction up to 3.3 and 5.4 times, respectively, at the maximum loading conditions.

Enhancing the security and reliability of power systems is of great significance to maintaining social stability. The power electronic devices of power systems can be utilized by attackers to launch indirect attacks, which could cause devastating impacts on the power grids. In this paper, load side attacks (LSAs) on relay protection devices is proposed as the first step to analyze the features of the attack. To achieve detection, a relation-based detection network is introduced to distinguish the LSAs from the normal faults.

We present experimental results for extending the 3-dB modulation bandwidth of an 850-nm vertical-cavity surface-emitting laser (VCSEL) with passive double transverse-coupled cavities (DTCC). The 3-dB modulation bandwidth of DTCC-VCSEL is 21GHz while that of a conventional VCSEL (C-VCSEL) fabricated in the same wafer is 12GHz. We realize eye-opening at large-signal modulations of 36 Gbps (NRZ) and 44Gbps (PAM4). Intensity fluctuations of single-transverse-coupled cavity (STCC)-VCSEL and DTCC-VCSEL were also examined at different bias currents under CW operations. The result shows a DTCC-VCSEL is more stable with lower intensity fluctuations.