This paper considers three pairs of circuit schemes for RF rectification. Given finite available power from RF source and load resistance, we formulate DC output power and efficiency of each scheme. Resultant formulas find that load-to-source resistance ratio R/r dominates the circuit performance. Maximum efficiency reaches 81.1% at R/r=1 for single-diode half wave rectifiers. It also reaches 92.3% for multiple-diode full wave ones at R/r=1.347 in bridge with capacitor, 0.742 in bridge with inductor, 5.389 in double-voltage, and 0.1854 in double-current topologies.

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A new power management scheme enables us to apply the power-gating technique to a 200-Gbps packet forwarding circuit. The circuit is equipped with two 100-Gbps forwarding engines (FEs), each of which processes inbound and outbound packets. When the amount of traffic decreases and only one forwarding engine is capable of processing all incoming packets, a packet-route switch installed in the data path routes all packets to one of the two FEs and the other FE is shut off. This technique reduces the power consumption by 14% when the total traffic rate is less than half of the maximum rate of 200Gbps.

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In this paper, a simple and accurate modeling technique that analyzes a non-rectilinear gate (NRG) transistor with a simplified trapezoidal approximation method is proposed. To approximate a non-rectangular channel shape into a trapezoidal shape, we extract three geometry-dependent parameters from post-lithographic patterns: the minimum channel length from the slices (L_min), maximum channel length from the slices (L_max), and effective channel width (W_eff). We slice the NRG transistor gate along its width, sort these slices according to their sizes, and then use trapezoidal approximation. A physics-based technology computer aided design (TCAD) simulation is used to verify our model in a typical 45-nm process. The developed model requires fewer computations and less runtime as compared to the previous approaches. Therefore, a full chip post-lithography analysis (PLA) becomes feasible.

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The DC open-loop voltage Gain is a very important specification for amplifiers. In order to increase this specification, in this paper, we have proposed an improved folded cascode gain boosted amplifier (improved FCGBA) which has extremely large DC open-loop voltage gain. Compared to traditional FCGBA, this novel structure needs only one auxiliary amplifier, so it is energy saving. Finally, with SMIC 0.18µm CMOS process of 1.8V supply and Hspice simulator, a corresponding amplifier with a capacitor load of 1.6pF is designed. Its voltage gain is 153dB; unit gain bandwidth is 1.91GHz; phase margin is 64°; 0.01% settling time is 2.36ns; and the power dissipation is only 12.9mW. This result confirms the validity of this new structure.

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A new type full digital ultra high frequency (UHF) radar system has been developed by Wuhan University to measure inshore wave. There is no analog mixer and local oscillator (LO) signal generator in the new system, Radio frequency (RF) is directly sampled, the pulse compression is fully completed in digital domain. The system operates at 340MHz with a widely frequency modulated (FM) bandwidth of 15MHz. Average transmit power is about 25 watts, and the maximum range over seawater will be more than 4 kilometers. The results of the field experiment on the coast of East China Sea presented here prove the feasibility of this system.

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This paper present a high throughput design for Sample Adaptive offset (SAO) filter and deblocking filter used in an HEVC decoder. A five-stage pipelined architecture is proposed to support both SAO filter and deblocking filter on a 32×32 pixel block basis. Deblocking filter and SAO filter can work simultaneously in consecutive pipeline stages. The on-chip SRAM can also be shared by deblocking filter and SAO filter. Coupled with the novel filter order, an interlaced SRAM memory mapping scheme is proposed to increase the throughput for deblocking filter. The experimental results show that our design can support 4K×2K@60fps (4096×2304) HEVC video sequence at the working frequency of only 60.8MHz.

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A 1.2V high conversion gain mixer which reuses the gm stage of the mixer as RF and IF amplifying stage is proposed in this paper. The gm stage of the proposed mixer converts the input RF voltage into current and also amplifies the down-converted IF signal. A high-pass network and a low-pass network are used in the mixer to block the RF signal and IF signal respectively in order to guarantee frequency stability. This mixer was designed and fabricated in 65nm CMOS process. The measured IIP3 and DSB NF are −16dBm and 13.5dB respectively. A high conversion gain of 30dB is achieved with the power consumption of 3mW under a 1.2V supply voltage.

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A shared aperture transparent MIMO antenna for smartphone is proposed in this study. Genetic algorithm (GA) is used to optimize the antenna geometry by interfacing Matlab tool and HFSS-EM simulator using visual basic (VB) scripting. The performance of transparent conducting film as an antenna element is enhanced through numerical simulation. An optimal antenna design is obtained through this optimization algorithm. The evaluated antenna’s electrical performance like VSWR, spatial correlation coefficient (SCC), and peak gain (dB) are desirable in the cellular frequency bands of 0.850GHz and 2.2GHz.

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This paper describes a design methodology for determining the number of stages in a cascaded time amplifier to minimize the area consumption. The total area consumption is categorized into three parts, which allows mathematical analysis and optimization to be performed. A combination of the proposed mathematical analysis and 2D mapping can determine the number of stages to minimize the area consumption.

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This paper presents a 6-bit current-steering DAC fabricated in 65nm digital CMOS process. In order to compensate for the systematic errors on the current sources, a novel switching scheme is proposed which can theoretically cancel out linear and quadratic gradient errors. Its implementation only requires reasonable number of current sources without increasing in the design complexity. The measured DNL and INL are 0.012LSB and 0.023LSB respectively. At the sampling rate of 1GS/s, 5.9bit ENOB and 51.4dB SFDR at Nyquist frequency are achieved.

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In NAND flash systems, the mapping table and related metadata information of FTL should be recovered from sudden power loss to provide data consistency. Nowadays, a lot of FTLs have been reported, however, there are little development reports for FTL recovery schemes. In this paper, we design fast metadata logging and recovery scheme to support efficient and fast power loss recovery. The designed recovery scheme is based on the page-level mapping FTL. In the designed FTL, All the metadata changes are logged into dedicated flash block, which minimize the frequency of metadata updates. At the recovery stage, only metadata blocks are retrieved. The designed FTL metadata logging and recovery scheme support fast sudden power loss recovery, with small amount of metadata logging overhead.

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