A simple high-order curvature-compensated technique for CMOS bandgap voltage reference (BVR) is presented and its advantage over the conventional ones is that this technique needs no extra circuitry for curvature compensation. The experimental prototype circuit is fabricated in CSMC 0.18µm CMOS process and occupies an area of 0.053mm². A temperature coefficient (TC) of 10.1ppm/°C is achieved with temperature ranging from -40°C to 120°C under 3V power supply. The line regulation of the output reference is only 0.85mV/V.

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The redundant data in integer motion estimation (IME) come from the overlapping reference blocks of consecutive current macroblocks processing, and thus increase the requirement of memory bandwidth. In order to overcome these obstacles, we propose the SRBIME (Shared Reference Block Integer Motion Estimation) and implement. In the SRBIME, one reference block is shared for parallel current macroblocks processing in order to enhance data reusability and to reduce internal memory on IME design. Experimental results show that the proposed motion estimation design saves 95.9% of external memory bandwidth than Inter-Candidate data reuse scheme, 3% of gate count and 11.8% of local memory are saved compared with previous design while supporting higher encoding specification.

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In this paper, a planar three-way power divider with compact size is presented using quarter-wave long five-conductor couple line. It is analytically proved that the proposed structure allows the performance of three-way power dividers. Based on the derived equations and simulation, the three-way power divider is designed and measured at 2.0GHz. The measurement shows excellent performance with insertion loss of 0.2dB, and return loss and isolation better than 20dB at a design frequency.

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Selected mapping (SLM) scheme without side information (SI) using specially designed phase symbols to reduce peak-to-average power ratio (PAPR) was recently published. The PAPR reduction performance was achieved at the cost of degraded bit error rate (BER) performance. This paper will present a new pilot phase symbol generation improving the PAPR reduction performance without BER performance deterioration.

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This paper proposes a new framework for managing large number of Video-on-Demand requests using the quad-tier hybrid architecture. This architecture provision four tiers to serve on-demand video requests and videos are mirrored to every tier based on a time-weighted popularity (TP) index derived from subscribers' log. Tier-1 Near-Server and Tier-2 Quasi-Server ‘broadcast’ most popular video while Tier-3 True-Server, located closer to subscribers, serve ad hoc on-demand video request using multicast protocol. Tier-4 Subscriber preloads frequently watch videos into the set-up-box for instantaneous playback. We propose suitable operational condition and evaluate the proposed TP index in the discussion.

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In this paper, the impact of negative bias temperature instability (NBTI) on dynamic logic circuits is analyzed and a design technique for a wide fan-in domino gate based on Genetic Algorithm (GA) optimization is proposed. In this technique, the degraded delay due to NBTI during the lifetime of the circuit is minimized subject to the constraints on area, power consumption and unity noise gain (UNG). The proposed optimization method is implemented in a 65-nm technology for a lifetime of 3 years. In comparison with a typical design, the optimized results show an improvement of more than 21.6% in delay during the circuit lifetime with a negligible change in the power and the UNG. The proposed method has the advantage that it can be used for any desired circuit lifetime with any reasonable constraints on design parameters, just with setting the corresponding parameters in the algorithm.

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This paper addresses robust estimation for the frequency offset of orthogonal frequency division multiplexing in non-Gaussian noise channels. We first propose a maximum-likelihood (ML) estimator in non-Gaussian noise modeled as a complex isotropic Cauchy process, and then present a simpler, yet still robust, estimator based on the ML estimator. From numerical results, it is confirmed that the proposed estimators offer a substantial performance improvement over the conventional estimators in non-Gaussian noise channels.

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An impact of longitudinal structural parameter drift on crosstalk behavior of multi-core fibers is investigated with a newly proposed semi-analytical method which can easily simulate crosstalk under the various kinds of parameter drifts. The simulation results indicate that the structural parameter drift has an important role in moderating bending diameter dependence of crosstalk of multi-core fibers.

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This paper presents a miniaturized 10/24-GHz rat-race coupler using synthetic transmission lines on a glass substrate. Compared to a standard CMOS process, the proposed CMOS-compatible glass substrate features lower substrate losses and thicker metal layers. The area-consuming transmission line layouts are implemented by the meandered synthetic transmission lines with high slow-wave factors and low losses. The coupler based on the synthetic TLs is designed, fabricated, and verified. Good agreement between the simulation and measurement is also observed. The chip size is merely 2.5 × 2.2mm² which is comparable to on-chip levels.

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In this paper, a novel technique to design bandpass filter, is presented. Defected Ground Structures (DGS) are used as the main block of the filter. Two filters with different center frequencies and fractional bandwidths with two different structures have been simulated designed and compared. By changing the dimensions of the structure, filter response can be easily controlled. Several useful graphs have been presented to design other filters. Three sections of DGS have been cascaded which improve the response of the filter.

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This letter describes an efficient architecture for the computation of fast Fourier transform (FFT) algorithms with single-bit input. The proposed architecture is aimed for the first stages of pipelined FFT architectures, processing one sample per clock cycle, hence making it suiable for real-time FFT computation. Since natural input order pipeline FFTs use large memories in the early stages, it is important to keep the word length shorter in the beginning of the pipeline. By replacing the initial butterflies and rotators of an architecture with that of the proposed block, the memory requirements can be significantly reduced. Comparisons with the commonly used single delay feedback (SDF) architecture show that more than 50% of the required memory can be saved in some cases.

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We report a polarization-multiplexed 10Gsymbol/s, 64QAM (120Gbit/s) coherent transmission over 150km by using an optical phase-locked loop (OPLL) circuit employing narrow linewidth LDs. The OPLL realized low phase noise demodulation of 64QAM signal. As a result, 120Gbit/s data signal were transmitted with a bit error rate (BER) performance below a forward error correction (FEC) threshold of 2×10^-3.

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A DC gain enhanced recycling folded cascode amplifier with a new positive feedback output stage is presented. The proposed amplifier using positive feedback to cancel the output conductance allows DC gain to be enhanced without affecting the bandwidth of the amplifier. The proposed amplifier was implemented in SMIC standard 65nm CMOS process. Simulation results show that a DC gain enhancement of 35dB is achieved without limiting the bandwidth.

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This paper presents a novel collision-less optical burst transmission scheme, namely, look-ahead optical burst transmission (LAOBT) for WDM ring networks. In the LAOBT, bursts are generated and inserted into burst streams by utilizing the void intervals of incoming bursts (IBs) in advance. The void size is estimated by splitting optical power into two paths, delaying one of the signals at the fiber delay line (FDL) and calculating IBs' residual time from the splitter to the optical cross-connect (OXC). The performance evaluation results show that our proposed scheme increases link utilization without significant increment of end-to-end delay and signaling overhead.

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