We measured improvement of five visual abilities by watching stereoscopic image. Kinetic visual acuity and depth perception were improved by 3.06% and 1.95% respectively compared with un-observing. In eye movement and near point distance, there is not nearly change. However, peripheral vision declined by 3.49%.

抄録全体を表示

The analytical temperature model of coaxial through-silicon-via (C-TSV)-based three-dimensional integrated circuit (3D IC) is developed based on the Fourier’ law of heat transfer and energy conservation, and is verified by employing ANSYS. Based on the theoretical model, several design guidelines are concluded. From the point of thermal management, 1) TSV should be inserted with high density; 2) Cu is a better material than Al and W; 3) the 3D IC layer should be as few as possible; 4) the silicon substrate thickness should be as thin as possible; 5) the temperature-sensitive modules should be placed near TSV and heat sink.

抄録全体を表示

This paper reports a novel wideband two-way power divider with improved out-of-band rejection based on substrate integrated waveguide (SIW) technology. Periodic radial line slots are etched on the bottom side of SIW to achieve the band-stop characteristic. The band-pass response is achieved by combing the band-stop characteristic of the radial line slots and the high-pass characteristic of SIW. An experimental circuit is fabricated by the traditional printed circuit board technology. The measured results show that the power divider has the advantages of wideband (about 42.8% with center frequency 7 GHz for Return Loss > 10 dB) and sharp roll-off skirts (better than 37 dB/GHz).

抄録全体を表示

This paper presents a new adaptable three-moduli set, {2^n+k, 2ⁿ − 1, 2ⁿ⁻¹ − 1}. It has three advantages for designing residue number system (RNS)-based digital signal processor (DSP) systems. First, it does not include a (2ⁿ + 1)-type modulo, thus providing a high-speed and low-cost system design. Second, three parallel DSP module channels achieve more efficient delay-balancing, thereby enhancing the system operation speed. Third, the set possesses an adaptable 2^n+k modulo for avoiding over-ratio problems and reducing the system hardware overheads. Through the implementation of a mixed-radix conversion concept, an efficient converter was derived for the proposed adaptable moduli set. For system evaluation and comparison, the proposed adaptable and related moduli sets were used to implement a 16-tap RNS-based finite impulse response module that contains a forward converter, FIR module, and reverse converter. Based on TSMC 90-nm CMOS process technology, all implementations were synthesized to obtain layout results for a performance comparison. The design derived using the proposed moduli set achieved a 12%–46% AD² (area × delay²) saving compared with those derived using other moduli sets or binary number systems.

抄録全体を表示

A LUT with Hierarchical Structure (HS-LUT) is proposed in this paper to realize the unique nonlinear component, Substitution Box (S-box), of the block ciphers. Different types of S-boxes are analyzed and four important features of them are summarized. Then, custom 4R/1W memory is proposed as the storage unit of the reconfigurable S-box, and an example set of block ciphers is put forward to describe how to achieve a satisfactory structure of reconfigurable S-box. The proposed HS-LUT is applicable for different sets of ciphers and it is implemented under TSMC 40 nm CMOS technology to compare with similar work. The comparison result shows that the proposed HS-LUT gains 6.88% to 51.76% area efficiency improvement.

抄録全体を表示

This paper presents a compact Wilkinson power divider with enhanced harmonics suppression. By replacing the quarter-wavelength impedance transformers in the traditional Wilkinson power divider with modified T-type impedance transformers (MTITs), three transmission zeros can be created at the second, third and fourth harmonic frequencies. The impedance transformers are folded to reduce the size of the power divider. For validation, a power divider operating at 1 GHz is implemented. Results indicate that the proposed structure can effectively be used for high order harmonics suppression while maintaining a good in-band performance and compact size.

抄録全体を表示

STT-RAM is an emerging memory cell to construct on-chip memories or caches. However, in advanced process technology, it is known that STT-RAM cells are vulnerable to read disturbance. To employ STT-RAM cells in on-chip caches for better energy- and cost-efficiency, appropriate techniques to prevent or avoid read disturbance are essential. In this paper, we propose a novel architectural technique to enable an energy- and performance-efficient STT-RAM based L1 instruction caches for future process technologies. Our selective way access with a write line buffer adopts a sequential cache access between the MRU way and non-MRU way, reducing energy overhead from the data restoring after the read operation. In addition, the write line buffer hides a latency of currently pending or on-going write operations in L1 instruction caches, minimizing stalls in processor pipelines. Our proposed techniques improve performance per Watt of the STT-RAM based L1 instruction cache by 1.6X and 2.6X compared to the conventional SRAM-based cache (denoted as SRAM in this paper) and STT-RAM based cache with the naive data restoring (denoted as STTRAM_dr in this paper).

抄録全体を表示

A dual single-pole double-throw (SPDT)/single-pole three throw (SP3T) distribution switch without the employment of negative voltage generator (NVG) for multi-mode multi-band applications has been designed and fabricated in a 0.18 µm silicon-on-insulator (SOI) CMOS process. To reduce power dissipation and prevent the noise from affecting the RF signal, an alternative bias strategy driven only by the positive voltage generator (PVG) is presented. Besides, LC impedance matching network are designed in both series and shunt branch to improve the insertion loss (IL) and isolation, respectively. For comparing the potential performance distinction, a switch version with conventional negative bias method is also implemented, which shows an IL of 0.41/0.65 dB and minimum isolation of 26.9/23.6 dB at 0.9/1.9 GHz, respectively. The presented switch adopting alternative bias scheme achieves improved IL of 0.37/0.53 dB and minimum isolation of 24.2/32.5 dB at 0.9/1.9 GHz, respectively. Both cases reveal comparative power handling capability and harmonic performance, while the active current consumption in the stand-by mode is significantly reduced with the new bias strategy.

抄録全体を表示

A novel double folded quarter mode substrate integrated waveguide (DFQMSIW) resonator is proposed. The dominant resonant mode of the proposed resonator is TE₁₀₁ mode. The size of the DFQMSIW cavity is reduced nearly by 94% compared with the conventional SIW cavity. A three order cascaded DFQMSIW filter with a center frequency of 2.84 GHz and a fractional bandwidth of 11.5% is implemented. The measured results show that the filter insertion losses are below −1.8 dB and return losses are better than −15 dB. Good agreement between simulated and measured results demonstrates the validity of the proposed method.

抄録全体を表示

Minimizing the interconnection length between the processing elements (PEs) of VLSI arrays is beneficial to reduce the capacitance, power dissipation and dynamic communication cost. In this paper, a novel method, based on integer programming, for constructing tightly-coupled subarrays from the degradable VLSI arrays is presented, such that the target array has the minimum interconnection length. Compared with the state-of-the-art algorithms, the proposed method can guarantee that the interconnection length of the target array is minimum in row and column directions simultaneously. The performances of the proposed method are compared with previous studies and it indicates that the proposed method achieves better results in terms of total interconnection length.

抄録全体を表示

We developed an optical gating device using a bulk layer and high mesa ridge/BH hybrid structure with input power of 14.5 dBm for optical communication performance monitoring. The shortest gating width of 3.9 ps was obtained in all-optical sampling experiments. However, gated waveform distortion occurred due to superfluous carriers in absorption layer in case of low bias voltage and optical pumping power condition. We have successfully improved waveform quality by extension electric parasitic capacitance to draw out it, thus variable gating width depending on transmission speed has been realized.

抄録全体を表示

This paper presents a 1∼3 GHz voltage controlled oscillator (VCO) with a rail-to-rail VCO tuning voltage (V_CONT) range. To obtain wide and linear V_CONT range, a new differential amplifier with a rail-to-rail common mode input range and an unstacked output stage is proposed. By using the proposed differential amplifier in the analog fine tuning block, V_CONT can span almost the rail-to-rail supply voltage with good linearity. For verification, a prototype VCO was fabricated in a 65 nm 1P7M CMOS process.

抄録全体を表示

In this article, a compact antenna is proposed using new microwave dielectric ceramic (MDC) substrate for 5G millimetre wave application. The distinctive novelties exhibited in this article are used of MDCs substrate material for antenna designing and performances analysis for wireless communication. The proposed antenna achieves impedance bandwidth of 2.66 GHz (from 27.235 GHz to 29.895 GHz), which covers the top interest (28 GHz) for 5G mm-wave in some countries and trials have been reported. The proposed antenna attains average gain of 5.44 dB and 93% of radiation efficiency with antenna size of 1.32λ × 1.32λ × 0.094λ.

抄録全体を表示

Canonical signed digit (CSD) encoding is applied to the COordinate Rotation DIgital Computer (CORDIC) algorithm. The closed-form expressions of angle quantization error are obtained and verified with the simulation results, showing that the CSD-based CORDIC algorithm improves the accuracy significantly if the rotation angle is decomposed appropriately. The VLSI implementation results show that the proposed CSD-based CORDIC algorithm remarkably reduces the execution time of the conventional CORDIC algorithm.

抄録全体を表示

A compact 16-bit chipless RFID moisture sensor tag with a size of 13.2 × 19.6 mm² is designed, fabricated and analyzed. The presented moisture sensor tag is realized on a paper substrate with silver nano particle based ink patches as conducting material. The frequency band of operation is 0.5 to 14 GHz having an overall bandwidth of 13.5 GHz. It is loaded with slots of different lengths and widths, etched on the conductive material. The tag exhibits stable sensing characteristic towards moisture in the real environment. The flexible, sensitive and environmental friendly nature of the proposed tag makes it suitable for wider, low-cost and organic electronics applications.

抄録全体を表示

A light-weight one-cycle EDAC (timing error detection and correction) technique is proposed to eliminate timing margins resulting from process, voltage, temperature and aging (PVTA) variations. The collaborative approach applies TEDPI (timing error deletion programming interface) to pre-detect most of the errors through an offline error prediction model, and pre-correct them at compilation time by using a specially designed error avoidance instruction. Experimental results based on a three-stage commercial processor show that TEDPI has improved peak performance of the traditional EDAC system by 15.6% and reduced the energy consumption by 4.4% with less than 0.71% area overhead.

抄録全体を表示

A novel compact microstrip ultra-wideband (UWB) bandpass filter (BPF) is proposed using a multiple-mode resonator (MMR), aiming at transmitting signals in the whole UWB passband. The resonant frequencies of this MMR in the design are properly adjusted equally within the UWB passband. Then, two aperture-backed interdigital coupled-lines at the two sides are introduced for an effective enhancement of the capacitive coupling factor. Transmission zeros can be created at the lower and upper passband edges to improve the passband selectivity greatly. Finally, a microstrip UWB filter with good in-band filtering performance and sharp rejection skirts is simulated and fabricated with good agreement.

抄録全体を表示