We propose a novel charge sharing bit-line 10T SRAM for differential read and single ended (SE) write. Decoupled read provides high noise margin. Read bit-lines are not charged to full V_DD, and these share charge for read 1 operation. A new write driver is proposed for SE write which charges the write-bit-line conditionally. Virtual power rail is used to suppress bit-line leakages. Compared with 6T SRAM, charge sharing scheme potentially consumes only 25% read and 50% write dynamic power. Thorough comparisons with 6T at 45 nm node show that the proposed 10T design has 2× read static noise margin, 71% reduction in total read and 48% reduction in total write power.

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To avoid the timing errors caused by the asynchronous control of elastic buffer between read and write operations. In this paper, a new skip (SKP) adding technology is proposed, which is achieved by the suspending of the read pointer. Based on the proposed new mechanism, a new elastic buffer is designed and realized under the TSMC65nm CMOS technology. The post simulation results show that, the presented elastic buffer can complete SKP adding and removing function correctly, and the clock frequencies can reach 500 MHz with tiny changes in area, energy consumption and speed of reading. It can be applied to the design and optimization of USB3.0.

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As a model for quantum computation, quantum circuits have found their wide applications in communications, cryptography and information processing. In order to synthesize arbitrary quantum circuits, we present a new type of gate called quantum multiplex rotation gate, which is implemented by simply elementary gates. A method based on QR decomposition and two optimization rules are proposed to decompose general quantum circuit acting on n-qubits into quantum multiplex rotation gates. In comparison with other synthesis algorithms by QR decomposition, our methods achieve better performance in terms of elementary gate counts, 1.2 × 4ⁿ approximately.

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A modified impedance network boundary condition (INBC) is proposed for modeling electrically thin conductive layers (TCLs) under plane wave incidence in finite-difference time-domain (FDTD) method. Compared to the conventional INBC which represents the relationship between the electric and the magnetic fields collocated at two faces of the TCL, the modified INBC takes into consideration both the half-space-cell and half-time-step difference of the electric and the magnetic fields in Yee’s grid. The primary advantage of the modified INBC is that it can be implemented in conventional FDTD algorithm without half-cell shift approximation. Numerical examples are presented to validate the efficiency and accuracy of the proposed method in analyzing thin layers with low conductivities.

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This paper presents a novel technique to enhance Antenna-on-Chip gain by introducing a high resistivity layer below it. Instead of using the costly ion implantation method to increase resistivity, the N-well that is available in the standard CMOS process is used. A distributed grid structure of N-well on P-type substrate is designed such that the P and N semiconductors types are fully depleted forming a layer with high resistivity. By an electromagnetic simulation, the using depletion layers enhance the antenna gain and radiation efficiency without increasing the occupied area. The simulated and measured |S11| are in fair agreement. The measured gain is −1.5 dBi at 66 GHz.

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Extending the dynamic range of analog-to-digital converters (ADCs) is an important issue in their application field. This paper presents a novel nonlinear equalizer based on the cube coefficient subspace (CCS) architecture to mitigate nonlinearities inherent in ADCs. The proposed equalizer is verified with a 14-bit, 200-MSPS ADC injected a two-tone signal. Simulation results show that it achieves a 16.55 dB improvement in dynamic range with a computational complexity of 110 operations per sample (OPS). The improvement using the proposed equalizer is 14.12 dB and 2.67 dB greater than those using two conventional equalizers: the memory polynomial (MP) and horizontal coordinate system (HCS) equalizers, respectively, with the same computational complexity.

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We investigated all-optical flip-flop operations with AND-gate functionality by injecting data and set inputs with different wavelengths to a 1.55-µm polarization bistable vertical-cavity surface-emitting laser. Control of the phase difference between the two inputs is not needed for stable operation, which differs from the same wavelength case we have used thus far. Thus, this proposed method will simplify all-optical signal processing systems. The wavelength difference dependencies of the switching power and the timing jitter of the polarization switching were measured for 1-ns data pulses. For 2 GHz wavelength difference, the data (set) pulse power was about −20 (−14) dBm and the timing jitter was about 110 ps. The BER was about 8 × 10⁻³.

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