In this study, the authors performed a computer experiment on Renesas SH4 and Intel PXA255, which are very popular CPUs for embedded use, to verify their floating-point operation performance in addition (subtraction) and multiplication. The experimental results show that outputs of the embedded CPUs have possible errors. The errors have been successfully removed by clearing the low-order 10bits to zero in the field of fractional bits of the floating point numbers. The result suggests that special care must be used in the accurate calculation when using an embedded CPU for floating point operations.

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This paper presents a system performance analysis of an optical single sideband system (OSSB) when drive level errors occur in the modulating signal driving the dual arm Mach-Zehnder modulator (MZM). The performance is evaluated in terms of the optical sideband suppression, frequency response and power penalty measurements. Experiments are carried out and a mathematical model of the OSSB system incorporating the drive level error is developed. The theoretical and experimental results suggest that the drive level error leads to reduced system performance as a result of poor received subcarrier power. The overall frequency response of the system, which is affected by drive level errors, accumulated CD and subcarrier frequency, has a direct influence over the power penalty. However, reduction in power penalty slope is observed at peaks of the OSSB frequency response.

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In this paper, a performance comparison of several proposed asynchronous pipeline styles is presented. The asynchronous styles include GasP, MOUSETRAP, IPCMOS, LP_SR2/1, HC, STFB, LDA, LP2/1, RSPCFB, and NCL. Both 4-bit and 16-bit 4-stage FIFO circuits are designed and simulated utilizing HSPICE. The simulation results are then used to compare the styles in terms of throughput, latency, power dissipation, transistor count, and datapath width. In addition, two figures of merit which relate the energy and the delay of the circuit are utilized in the comparison of the styles. To estimate the throughput and the latency of the circuits, a simple analytical model for the transistor delay is also proposed. The predictions of the analytical model for the throughput and the latency are compared to the simulations results to assess the accuracy of the model.

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A fast synchronous acquisition method which is applied to Direct Optical Switching-Code Division Multiple Access (DOS-CDMA) scheme in Software Definable Radio Networks (SDRNs) is proposed. This paper shows that the chaotic synchronization enables to reduce synchronous acquisition time in DOS-CDMA scheme compared to the sliding correlation method.
In case that code length is 121, reduction effect of synchronous acquisition time of 95% is obtained by the computer simulations.

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This paper proposes a novel approach for the implementation of Distributed Video coding (DVC) using 4-PSK turbo trellis coded modulation (TTCM). We have adapted the TTCM concept for source coding by generating parity at the encoder and transferring the symbol mapping to the decoder. The parity bits are sent to the decoder with puncturing as in a turbo based DVC codecs and combined with side information to form the symbols used in the TTCM decoder. The side information is generated by basic frame interpolation. The proposed codec was tested with different test video sequences and the results obtained show up to 6dB improvement in PSNR with less memory for the same bit rate when compared with the turbo coding based DVC codecs.

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