The recently-developed digital coherent receiver enables us to employ a variety of spectrally-efficient modulation formats such as M-ary phase-shift keying (PSK) and quadrature-amplitude modulation (QAM). Moreover, in the digital domain, we can equalize linear transmission impairments, which may stem from group-velocity dispersion (GVD) and polarization-mode dispersion (PMD) of fibers for transmission, because the phase information is preserved after coherent detection.
This paper reviews the history of coherent optical communications, the principle of coherent detection, and the concept of the digital coherent receiver. After that, we discuss digital signal processing (DSP) for mitigating transmission impairments, coherent transmission characteristics of multi-level optical signals, and future prospects of coherent optical communications.

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We review our recent progress toward transmission speeds per channel of 100Gbit/s and beyond, focusing on optical modulators and receivers for coherent transmission using PLC integration technology. We have used PLC-LiNbO₃ hybrid integration technology to develop optical multilevel modulators, including a DP-QPSK modulator and a 64QAM modulator for 100Gbit/s and post 100Gbit/s. This technology provides practical performance and scalability for various advanced modulations. We have also developed flexible-format modulators for future elastic networks, which will enable the efficient use of the spectral resource. This modulator can select an optimum carrier number and modulation level according to the transmission conditions. In terms of receivers, we have developed integrated optical receiver front-ends for 100Gbit/s DP-QPSK based on hermetically sealed O/E converters. PLC hybrid-integration technologies are promising for compact, practical, cost-effective, and highly reliable coherent optical modulators and receivers.

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This paper describes optical quadrature amplitude modulation techniques using parallel Mach-Zehnder modulators (MZMs). Arbitrary constellations of optical signals can be generated by using a dual-parallel MZM which can independently control real and imaginary components of lightwaves, where each MZM should be driven by multi-level electric signals. Many parallel MZMs, such as quad-parallel MZMs, octet-parallel MZMs can synthesize optical multi-level signals from binary data stream generated by electronics designed for binary modulation formats. We also investigate characterization methods of parallel MZMs. Precise measurement of half-wave voltage, extinction ratio and chirp parameter of each MZM element can be achieved by using optical spectrum analysis.

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During video transmission, errors may happen normally. Addressing error resiliency, the reference modification (RM) approach at video compression encoder is used to modify the original reference to a modified one, which is less sensitive to errors. Apparently it is a bit rate overhead compared to original reference based conventional encoder. Therefore to reduce such bit rate overhead while still keep the error resilience performance is a big issue. A low bit rate overhead based RM approach is proposed in this paper, where the decoder information is exploited to perform encoding. In the proposal, the modified reference has more correlation to original reference, thus can reduce the bit rate overhead. In addition, the proposal can achieve better image recovery compared to existing works, and still be compatible to standard decoder. Overall, the proposal provides the best trade-off among the error resiliency, coding efficiency, and standard compatibility.

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A microstrip-fed printed monopole antenna having band-notch characteristics is proposed. The fullband antenna introduces 2.5-10.6GHz bandwidth covering the FCC frequency band for UWB applications. Six inverted L-shaped stubs on the bottom of the substrate, which are connected to the radiating patch through via pins, are used to create flexible multi-band filtering function. Using this technique it is possible to reject one to six different frequency bands.

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This work proposes and analyzes an intuitive time-distributed procedure for estimating the effective number of bits (ENOB) of ADCs during the design phase. Two derived numbers, the ENOB lower-bound and the ENOB upper-bound, signal to a designer whether the design has satisfied the desired quality, or either further circuit improvement or a more accurate time-distributed procedure is necessary. The result enables designers to employ the procedure to almost linearly reduce the ENOB simulation waiting time with a controllable loss of accuracy. Two successive approximation register (SAR) ADC designs demonstrate the effectiveness of the procedure, one of which has been manufactured.

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To reduce the contact resistance between the silicides and source/drain diffusion regions in scaled MOSFETs, the contact resistivity of barrier height controlled Pt_xHf_1-xSi to heavily doped Si was investigated by the cross-bridge Kelvin resistor method for the first time. Pt_xHf_1-xSi was formed from the in-situ deposited Pt(8-12nm)/Hf(2-8nm)/Si(100) stacked structures followed by the 400°C/60min silicidation in N₂ ambient. The obtained Schottky barrier height (SBH) for electron was 0.53eV in Pt_0.6Hf_0.4Si/n-Si(100), while the SBH for hole in Pt_0.9Hf_0.1Si/p-Si(100) was 0.26eV, respectively. The contact resistivities of 2×10^-7Ωcm² for Pt_0.6Hf_0.4Si/n⁺-Si(100) and 7.1×10^-8Ωcm² for Pt_0.9Hf_0.1Si/p⁺-Si(100) were achieved even for the minimum contact area of 4µm².

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Synthetic Aperture Radar (SAR) is widely known as a high resolution imaging system in microwave remote sensing. Large number of frequency-modulated received echoes must be acquired in real time. A typical SAR data acquisition unit (DAQ) involves high speed analog-to-digital conversion, front-end pre-processing, and data recording. Subsequent processes consist of computationally intensive digital signal processing for image formation. In this paper, an efficient data acquisition and SAR processing method is proposed. It is based on a modified discrete Fourier Transform algorithm, which requires lesser system's computational load as compared to conventional Fast Fourier Transform. The proposed system has been implemented on an UAVSAR (Unmanned Aerial Vehicle SAR) and the flight tests have shown promising results for real-time imaging.

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This paper proposes a hybrid shortened transmission/expanding reception technique and single carrier modulation with a zero forcing frequency domain equalizer when a single carrier modulation with a guard period is transmitted. Regarding single carrier transmission data as shortened OFDM transmission data allows an expanding reception technique and a maximum ratio to be combined in the receiver, and a parallel single carrier modulation with a frequency domain equalizer is used as a secondary receiver. The proposed hybrid scheme does not have channel codec but simulation results show it has better performances in comparison with the coded OFDM algorithm at the expense of algebraic calculations and FFT executions.

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A successive approximation register (SAR) analog-to-digital converter (ADC) with an integrating resolution booster (IRB) is proposed and experimentally verified to provide the capability of dual-mode operation, that is, low-power and high-resolution modes. This dual-mode architecture corresponds to a kind of hybrid ADC architecture, combining a low-power SAR ADC and a high-resolution integrating-type ADC together. A prototype ADC design is fabricated in a 0.18µm CMOS process, and its dual-mode operation is experimentally verified. The total power consumption in the low-power mode was only 8µW with the resolution of 6bits, and the high-resolution mode achieved an additional resolution of 4bits by activating the IRB, consuming the instant power of 380µW.

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The paper presents a digital pulse compression approach for high frequency (HF) chirp radar. The emphasis is to accomplish echo signal de-chirp operation by modified orthogonal transformation on field programmable gates array (FPGA) chip. This approach has been developed for an all-digital receiver platform which is directly radio frequency (RF) band-pass sampling, compared with the traditional analog receiver or intermediate frequency (IF) receiver, it has an easy hardware structure closing to a “soft” radar mode. The system closed-loop test shows the correctness and rationality of the design, meeting the demand of engineering application.

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A new hybrid multicast deadlock-free scheme is proposed to enhance the multicast capability. In the proposed scheme, the small-sized multicast packet is routed in a deadlock-free way by packet-buffered and asynchronous replication, and the large-sized multicast packet is transferred under the control of centralized allocator, which restricts the number of concurrent multicast with large-sized packet transmission. The virtualization at the Network-on-Chip (NoC) level is also taken into consideration, that the allocator reserves respective counters for each sub-network. According to result of the experiment under the real workload traces, the performance reduction caused by centralized allocator is negligible. The router and the allocator are synthesized in Chartered 90nm CMOS technology. Compared with the only packet-buffered scheme, the allocator only consumes extra 0.079% to 0.2972% area overhead according to the different setting (routing mechanism, network size, number of supported sub-network) while offering the ability of large-sized multicast packet transmission.

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A high DC gain, wide band and fast settling fully differential amplifier is presented. The pole zero cancellation technique is used in order to increase the band width of the OTA. Also, a new technique for pole zero cancellation in three-stage OTAs is presented. The proposed OTA simulated in standard TSMC 0.18µm CMOS technology with a 1.8V power supply. The DC gain of the OTA is 85dB, the unity gain band width is 740MHz and the phase margin of 60 degree is achieved. The amplifier consumes only 18.8mW.

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