A linear frequency modulated continuous wave (LFMCW) radar is introduced to localize the impedance discontinuities on the instrument cable used in nuclear plants. The LFMCW reflectometry uses a phenomenon that electromagnetic pulses are reflected at the impedance discontinuities to localize impedance discontinuity points on the cable. For localizing impedance discontinuities, time delays between the incident signal and the reflected signals from the impedance discontinuities have to be measured. The LFMCW is modeled by time-varying auto-regressive (AR) model. From the coefficients of the AR model, instantaneous frequency is estimated by the Kalman filtering to calculate the time delays. The performance of the proposed method is verified by experiments.

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A low-voltage current-mode integrator is presented for a continuous-time baseband channel selection filter of wireless communication systems. Fully-balanced current-mirror structure with additional cascode transistors operated in linear region enables low-voltage and low-power dissipation properties as well as voltage-controllable cut-off frequencies over a broad frequency range. A channel selection filter using the proposed integrator for three different communication standards with direct conversion receiver is implemented for a design example. Experimental results show that the implemented channel selection filter achieves design specification and outperforms other conventional filters.

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S-box is a core component of many block cipher algorithms. A reconfigurable S-box based on look-up table (LUT) with memory-sharing is proposed in this paper. It uses a sharing memory to support different S-box operation modes (4 × 4, 6 × 4, and 8 × 8) for most of the block cipher algorithms as well as reduce memory size. It also supports high-speed pipeline structure of DES and Serpent. This new type of S-box is applied in a reconfigurable cryptographic coprocessor under 0.18μm CMOS process. It is also used in a DES circuit with 16 pipeline stages. Synthesis results show that it works at 100MHz frequency with flexibility of different modes and a reduced area compared to non-memory-sharing LUT method with equivalent sizes of different S-boxes.

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A successive approximation time-to-digital converter (TDC) is presented. The proposed TDC is based on the vernier charging method, and characterized with its timing resolution independent of the period of the reference clock. Further by including voltage ratio together with both current and capacitor ratios to enlarge the pulse stretch factor, a higher timing resolution is attained. The circuit is implemented in a 130nm CMOS process and occupies an area of 0.32×0.21mm². According to the simulation results, the proposed TDC achieves typically 6.25ps resolution and consumes 0.9mW from a 1.5V supply voltage.

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Although NAND-based block devices offer good average performance compared to hard disk drives, their poor worst-case performance can be a serious problem in servers and real-time systems. In order to address it, this study proposes to use an active log pool to isolate the working sectors of each process to different NAND blocks. Doing so reduces the association degree of log blocks, which in turn reduces the worst-case write latency. A trace-driven simulation shows that the worst-case latency is reduced up to 1/9 compared to the original scheme without hurting the average performance severely.

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