With the technology scaling, the charge sharing effect is becoming more prominent. Using the property of DICE latch, we present a DICE-based test structure to measure the strength of charge sharing effect. Three-dimensional TCAD simulations are done to simulate the DICE property. And a test chip is fabricated by the commercial 65 nm bulk CMOS process to verify our proposed test structure. Heavy-ion experiment results indicate that this test structure is efficient to obtain the strength of charge sharing effect.

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Undesired points of operation i.e. real pole in the right half of s-plane causes relaxation oscillation, especially in GHz-range of monolithic oscillators. They also prove to be ‘hard’ target for most of the very powerful circuit simulators, like SpecterRF for example. Since the behavior is best described by the Eigen values of characteristic polynomial, then we settle on investigating the operating points using the time varying root locus (TVRL) method. The numerical QZ algorithm has been practiced to compute the characteristic roots relative to periodic steady-state (PSS). The circuit is modified to avoid relaxation process and it confirms the proper sinusoidal operation of oscillator.

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This paper presents a novel dual-band Wilkinson power divider, which contains two symmetric stepped-impedance dual-band inverters. The proposed circuit has very simple structure that only one isolation resistor is used, and is particularly suitable to be designed with large frequency ratio in compact dimensions. Detailed design formulas are derived. For verification, a dual band power divider with frequency ratio of 5.2 is designed and fabricated. The experimental results agree well with the simulation, demonstrating the features.

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This paper proposes a low-cost implementation of a multi-channel FIR filter on FPGA, where each channel can have variable bandwidth and coefficients. New structures of the tapped-delay line and the coefficient bank unit based on time-division multiplexing are proposed. Pipelined adder tree is used to expedite the filtering process without disturbing generation of control signals for multi-channel data access. From implementation results, it is found that the proposed 39-tap FIR filter involves 32% less number of slice registers as well as 65% less number of DSP blocks than the Xilinx FIR Core 5.0, and also supports variable bandwidth.

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Bypassing emerged as a performance improvement method for shared Last-Level Caches (LLC) in multicore processors where large data portions are never reused, wasting system resources. This paper proposes an alternative method to predict data bypassing using Support Vector Machine (SVM). Based on access traces obtained from a simulator, SVM is trained to generate bypass models which are integrated into the simulator to quantify LLC performance improvements. Results show that SVM can classify which data to bypass, improving LLC performance, achieving an average 6.72% miss rate decrease across SPLASH2 benchmark combinations.

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Evolvable hardware has been applied to the design of combinational logic circuits. But it usually takes too much time using evolutionary algorithm directly, especially designing large scale circuits. In this paper, a novel hybrid repair strategy is proposed, which is a combination of evolutionary repair method and Quine_McCluskey repair technique. Based on the hybrid repair strategy, an evolutionary algorithm is presented for the designs of combinational logic circuits. The experiment results demonstrate that the evolutionary algorithm proposed in this paper can keep balance between the time cost and gates consumption very well, and consumes fewer gates than the previous works.

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The damage production induced by swift heavy ion irradiation in bilayer graphene (BLG) is investigated by molecular dynamics method. By given energy to a cylindrical region, the carbon chains even nanoholes can be produced, which depends on the electronic energy loss (dE/dx). For BLG, the minimum value needed to generate defects lies in 5–7 keV/nm. A low density core and a high density shell structure can be seen while the radii of tracks are obtained. With increasing the values of dE/dx, the track radius is first increasing and then saturates. The analysis of defects indicates that only a small part of the defects can be recombined and the radiation damage in BLG is less severe than in single layer graphene.

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In this paper, we first propose two multicast partitioning methods named TBP (two block partitioning) and LBP (layer block partitioning), each of which has a different level of efficiency in 3D bufferless network on chip. In addition, we present a Recursive Partitioning (RP) method in which the network is recursively partitioned until all partitions contain comparable number of multicast destination nodes. By this method, the multicast destination nodes are distributed evenly and the network latency is significantly decreased. Simulation results illustrate that the RP scheme achieves 39%, 45% and 41% less latency on average than that of the TBP scheme and 8%, 17% and 12% less latency on average than that of the LBP scheme under three synthetic traffic patterns respectively.

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In this paper, the generation mechanism of single event upset reversal (SEUR) between 2 PMOS in SRAM cells is studied in depth based on 45 nm CMOS technology. We find that SEUR not only depends on the charge sharing but also follows the rule that the charge collection of passive device is larger and longer than that of active device. Based on SEUR generation mechanism, two novel layouts named Drain-Source-Drain (DSD) and Dummy are proposed to increase the rate of SEUR for reducing SEU vulnerability of SRAM cells. Compared with the traditional layout, DSD and Dummy layout reduce 4.26% and 31.56% SEU sensitive area under normal incident, respectively. For tilted incident, Dummy layout sharply increases SEUR rate while DSD layout is not better than the traditional layout on enhancing SEUR. Consequently, the proposed Dummy layout can improve SEU reliability without area penalty.

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We develop a simplified configuration of optical correlation- (or coherence-) domain reflectometry (OCDR) using a polymer optical fiber (POF). The conventional reference light path is removed by using as reference light the Fresnel-reflected light caused at the interface between a silica single-mode fiber and the POF. We demonstrate its basic operation and investigate the dependences of the spatial resolution and signal-to-noise ratio (SNR) on the sweep time of the laser modulation frequency. The optimal sweep time is found to be 30 ms (corresponding to a repetition rate of 33 Hz), at which both the resolution and SNR are maintained at high values.

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A full Ka-band in-line suspended stripline (SSL) to rectangular waveguide transition is proposed in this paper. The antisymmetric probes are introduced to transform the quasi-TEM mode of the SSL to the TE10 mode of the rectangular waveguide. Two slots with polygonal shapes are cut on the two probes respectively to improve the bandwidth of the transition. To verify this design, a back-to-back structure is fabricated and tested. The experimental results show that the insertion loss of better than 0.32 dB and the return loss of more than 14.2 dB are obtained from 25 to 40 GHz. The measurement results agree well with the simulations.

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Coaxial-annular through-silicon via (CA-TSV) is a novel TSV structure. In this letter, the thermal stress and keep-out zone (KOZ) of Cu and SiO₂ filled CA-TSV are studied, considering anisotropic property of silicon. Firstly, by employing ANSYS software, the CA-TSV-induced thermal stress is simulated and analyzed. Secondly, by evaluating the effects of thermal stress on carrier mobilities of pMOS and nMOS channels, the KOZs induced by CA-TSV is estimated and compared with those of coaxial TSV (C-TSV), for the cases of transistor channels along [100] and [110] orientations. It is proved quantitatively that CA-TSV has better thermo-mechanical performance than C-TSV.

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A single-event transient (SET) hardened LDO using novel structure is proposed to enhance the single-event effect tolerance. The novel LDO with built-in filter can mitigate the response of the sensitive nodes of circuit. If the SET pulse current flows through the sensitive nodes, the maximum variation of the output voltage is only 15.5 mV. In addition, the transient performance is slightly dropped back as a tradeoff for the built-in filter. When the workload changes transiently between 100 µA and 100 mA in 100 ns, the undershoot is 28.4 mV and the overshoot is nearly 20 mV with imperceptible peak.

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This work presents a K band two stage compact CMOS low noise amplifier (LNA) with closely placed two load inductors without guard rings. Unwanted proximate magnetic coupling between load inductors is carefully analyzed and affirmatively used to enhance the gain without impairing the stability. The fabricated compact LNA has a measured peak gain of 15.42 dB at 24 GHz, with the size of 650 µm × 550 µm, and consumes 10.8 mW from 1.2 V supply.

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