In this work we present a sub-1V pulse-width-modulation (PWM) CMOS image sensor. Ultra-low power consumption is achieved through the sub-threshold pixel bias, time-to-digital conversion and the array-level asynchronous counter. The 2-step readout scheme is adopted to improve the frame rate up to 68 fps. The prototype chip with 64 × 64 array has been fabricated in a 0.18 µm 1P6M CMOS process. Minimum functional analog supply of 0.36 V can be achieved, and the whole chip consumes only 1.14 µW at 13 fps, or 21.4 pW/frame-pixel. The dynamic range and FPN are measured to be 70 dB and 0.49% respectively.

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Conditional termination check min-sum algorithm (MSA) using the difference of the first two minima is proposed for faster decoding speed and lower power consumption of low-density parity-check (LDPC) code decoders. Judging from the size of the difference in LDPC decoding scheduling, the proposed method dynamically decides whether the termination checking steps will be skipped or not. The simulation results show that the decoding speed is improved up to 7%, and the power consumption is reduced by up to 16.43% without any loss of error correcting performance. Also, the additional hardware cost of the proposed method is negligible compared to conventional LDPC decoders.

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A power model for digital circuits with clock gating is proposed. The power states are defined by the values of clock gating enable signals. The power consumption for each power state is characterized by the low-level power analysis results. Experimental results show that the proposed power model achieves about 400 times faster analysis speed with less than 1% of error on average comparing to gate-level power models.

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For wireless power transfer (WPT) application with multi-load or multi-repeater, the system must need some inductance coil possessing the characteristic of transmitting power to multiple directions. This paper proposes a novel three-dimensional hexagon coil with simple structure, which is fabricated conveniently and easy to conformal with surrounding environment. The formula to calculate self- and mutual-inductances for the coil are given with the direction feature also introduced. Furthermore, numerical simulations and experimental results show mutual inductance is very stable in a wide scope of direction angle, to be applied in WPT with multi-directional transmission characteristics.

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In this paper, main and peaking voltages of a Doherty power amplifier are derived by means of the chain parameters of the output section to analyze the effect of the offset lines on the drain efficiency. It is shown that the main branch offset line dominates the drain efficiency. Furthermore, it is exhibited that moderate offset mismatch at the peaking branch has no significant influence on the output power performance of the amplifier. A 100 W GaN Doherty power amplifier is realized to experimentally verify the results.

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In this letter, a broadband coupler is presented that makes use of a corrugated half mode substrate integrated waveguide (CHMSIW) technique using a printed circuit board process. The coupler is realized by parallel CHMSIW lines where the vias to form the sidewalls of the HMSIW are placed with the open-circuit quarter-wave-length microstrip stubs and the energy couples by magnetic field. Compared with conventional SIW coupler, it is easily integrated with active devices because it can isolate better the CHMSIW input/output ports from the ground plane. The coupler is simulated and measured at 9.5–17.5 GHz. The result of measurement shows a good agreement with the result of simulation.

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This paper presents a novel current-biased voltage-programmed pixel circuit with low temperature polycrystalline silicon thin film transistors (LTPS-TFT) for active-matrix organic light-emitting diode (AMOLED) displays. The proposed 3T1C pixel circuit features a voltage data line to program pixel, and a fixed current source to compensate for non-idealities. In addition, the aging problem of the OLED could also be alleviated by the AC driving method. The simulation results indicate that the driving current has a deviation of less than 3% for ±0.5 V threshold voltage variation. Besides, it is also demonstrated that the high driving speed can be realized by increasing the bias current.

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This letter reports a column-parallel clock skew self-calibration circuit for time-resolved (TR) CMOS image sensors. In TR CMOS imagers, as the time resolution increases, the skew of gating clock between pixels becomes a difficult problem because the clock skew causes the reduction of measurable maximum range in particular pixels or unmeasurable pixels. To calibrate the skew in short time, a column-parallel skew self-calibration circuit based on two-stage delay line and a dual clock tree is proposed. The experimental results show that the skew calibration circuit successfully reduces the skew from 247 ps_rms to 25 ps_rms, and the calibration time is only 12 µs, which is much faster than the previous work.

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Wide-bandgap power devices such as those made from silicon carbide (SiC) and gallium nitride (GaN) offer superior electrical performance over conventional silicon (Si) devices for high-voltage applications. Their fast switching operation and low switching losses help increase the efficiency of power conversion circuit. This study focuses on the switching characteristics of a GaN Schottky barrier diode (SBD) and investigates the conducted noise characteristics in a DC–DC boost converter by comparing a Si PiN diode and a SiC SBD.

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We propose a novel and simple carrier recovery method from carrier-less phase modulated optical signals. In this method, homodyne detection of the received signal, modulation stripping by an electro-optic phase modulator, and injection locking of a laser diode for carrier generation are performed in a feedback loop. Carrier extraction and error-free homodyne detection of a 10-Gb/s RZ-BPSK signal is demonstrated. The method can also be extended to carrier extraction from QPSK signals.

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A reliability improved synchronous boost converter with spike suppression circuit is proposed in this paper. Compared with the traditional boost converter, a novel control circuit is designed to suppress the voltage spike at node SW during the dead time. In addition, the two main power switches could be avoided to operate in ON state during the transient process. Hence, both the reliability and the efficiency are improved. The converters with/without spike suppression circuit are designed and implemented in a 0.5 µm standard CMOS processes. The experimental results show that the voltage spike at node SW is reduced 43% when the load current is 0.5 A, and the efficiency is improved at light load.

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In this letter, a normally-off AlGaN/GaN MIS-HEMT using fluorinated gate dielectric was presented. The fluorine ions were injected into the Al₂O₃ gate dielectric to obtain positive threshold voltage (V_th) as well as avoiding the plasma induced to the GaN channel layer. Moreover the maximum transconductance of fluorinated gate MIS-HEMT has been improved compared with the non-treated MIS-HEMT. Furthermore, the fluorine ions injected into the Al₂O₃ gate dielectric could decrease the trap states density (D_T) and time constant (τ_T) at the Al₂O₃/GaN interface. The normally-off MIS-HEMT showed a very high drain current of 507 mA/mm and V_th of 0.6 V.

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Nowadays multi-functional wearable devices generally require high current drive capability because microcontrollers (MCU) or rechargeable batteries are embedded inside. To achieve both high current and high power efficiency, this article presents a switched-inductor-based AC-DC buck converter that is implemented on a 0.18 µm chip manufacturing process for transcutaneously powered wearable devices. Different from multi-stage AC-DC converters that were widely used for wearable devices, the presented single-stage circuit has concise structure but provides flexible voltage output, high efficiency, and high current drive capability. The maximum output current can go up to 250 mA, and the peak efficiency is measured as 80.1% for 100 mA load current. The chip size is 185 µm × 260 µm.

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Fully in-situ formation of Hf-based metal-oxide-nitride-oxide-silicon (MONOS) structures utilizing electron-cyclotron-resonance (ECR) plasma sputtering was investigated for the first time. It was found that the MONOS structures with in-situ formed HfN_0.5 gate electrode showed faster programing, high injection efficiency and larger flat-band voltage (V_FB) shift of 2.5 V compared to the MONOS structure with ex-situ formed Al gate electrode under programing voltage of 10 V. The retention characteristics of MONOS structure with in-situ formed HfN_0.5 gate electrode were also superior to the MONOS structure with ex-situ formed Al gate electrode. The degradation of retention for V_FB shift after 60 min of programing was 40% for the MONOS structure with ex-situ formed Al gate electrode, while it was 16% for the MONOS structure with in-situ formed HfN gate electrode.

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