This work proposes a Digitally Enhanced Low-Drop Out Voltage Regulator (DE-LDO) for Ultra High Radio Frequency IDentification (UHF RFID) passive tags. The DE-LDO design approach is based on the Finite State Machine (FSM) nature of the tag Digital Control. Injecting part of the FSM unconsumed current into LDO loop to enhance transient response, a more flat output voltage is obtained. Chip measurements shows that DE-LDO consumes a quiescent current of 600 nA at 1.6 V, delivering an output current and voltage of 8 µA and 1.2 V; a 69.76% Power Efficiency (PE) is observed. Circuit design and fabrication were performed using 0.50 µm CMOS technology.

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A power supply circuit that compensates for the voltage drop in the large-sized AMOLED display panel is presented. The voltage drop, which degrades luminance uniformity, is directly detected, and the detected value is then fed back to the controller circuit to adaptively adjust the power supply voltage in order to minimize the voltage drop. The validity of the proposed technique was verified by experimental results; the two-fold improvement was achieved in terms of the measured voltage drop. As a result, the measured luminance uniformity was also significantly enhanced.

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Three-dimensional (3D) memory stacking technology is one of the most promising technologies providing massive memory bandwidth, and thereby provides an opportunity to overcome performance bottlenecks in memory systems. In this paper, we analyze the performance of well-known efficient memory components such as stream buffer, L2 cache, and victim cache in order to exploit the massive memory bandwidth of the 3D stacked memory system. This paper also presents a method to determine the optimal memory capacity with the best performance efficiency (a.k.a. performance improvement efficiency (PIE)) and proposes a cooperative cache memory (CCM), which prefetches adaptively according to the memory access pattern in order to exploit the massive memory bandwidth of a 3D stacked memory system. The proposed CCM with a 512 KB L2 cache and 256 KB stream buffer with the proposed prefetching mechanism can deliver superior performance by about 13% over a conventional 8 MB L2 cache.

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A single-inductor, dual-input, and dual-output boost converter harvesting thermal and solar energy with a novel time-multiplexing maximum power point tracking (MPPT) algorithm is proposed in this paper. The proposed boost converter harvests energy from thermoelectric generator (TEG) and photovoltaic cell (PV cell) and applies the harvested power to the load and battery. The proposed MPPT algorithm controls the effective frequency of energy harvesting from TEG and PV cell by time multiplexing. As a result, the MPPT can be achieved using a single system clock frequency. The reduced number of required system clock frequencies can leads to power and area savings owing to the reduced clock generation circuits. The proposed boost converter is designed using 65 nm CMOS process technology and evaluated using the HSPICE simulation. The peak power conversion efficiency of the proposed boost converter is 78%.

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This work presents a nonlinear model for Junction Field-Effect Transistors (JFET) that is suitable for audio emulations in real-time. The model is implemented by using Wave Digital Filters (WDF), which offer accurate and real-time capability on digital processors. As emulation examples, a common source amplification stage and an electric guitar preamplifier are implemented in real-time in a reconfigurable Field Programmable Gate Array. For verification purposes, the WDF simulations were compared with the ones obtained by SPICE circuit analysis software. It is demonstrated how the JFET model and the emulation examples accurately work in real-time, matching the harmonic content of the reference SPICE simulations.

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This letter presents a novel low cost through-the-wall SMA connector and the transition structures from the SMA to a grounded coplanar waveguide (GCPW). The SMA connector has two short metal legs extended from the outer conductor used to reduce the discontinuity of the transition. The parameters of the GCPW are designed to match the geometry of the coaxial. A matching stub is introduced in the center conductor line to further improve the performance of the transition. A prototype device is developed and measured. The measurement results show the return loss of the proposed transition is better than 20 dB up to 26.5 GHz.

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We present a superconducting single-flux-quantum (SFQ) mask ROM comprising 2-bit storage cells and a sequential-access driver. Four types of storage cells for 2-bit data (“00,” “10,” “01,” “11”) are adopted for reduction of the cell dimensions, whereas the sequential access is suitable for a single-chip quantum voltage waveform generator implemented with an SFQ-based digital-to-analog converter. 2-bit storage cells of 60 × 70 µm² are fabricated using a niobium integration technology and tested in liquid helium. Operation of a sequential-access mask ROM with data of 8 bits × 6 words is also demonstrated.

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This letter presents a design approach for a bandpass filter (BPF) using a novel triple-mode stripline resonator. We clarify the external Q factor with respect to the cutout size of the center conductor and feed-line position, to establish the design approach. It is found that external Q factors of each mode is handled respectively. From those results, a triple-mode BPF is designed and fabricated. The experimental results agree with the simulation results and accordingly it is confirmed that a design approach was established.

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The static random access memory (SRAM) is indispensable for high performance applications. With technology scaling, the device size as well as the operation supply voltage (VDD) is reduced. However, with the supply voltage decreasing, the performance of the conventional 6T SRAM is deteriorated seriously. In this letter, a symmetrical 10T SRAM with dramatically improved read stability and write ability is proposed. The simulation results indicate that, compared with the conventional 6T SRAM, the read static noise margin (RSNM) and write margin (WM) of the proposed 10T SRAM achieve 2.43× and 4.51× improvement, respectively, at a 0.8 V supply voltage in SMIC 65 nm technology. As a result, lower failure probability in access operations is expected. Moreover, the minimum supply voltage (VDD_min) of the proposed 10T SRAM achieves ∼0.32× compared with that of conventional 6T cell. Additionally, it also shows a better tolerance to the varying process variations.

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Direct optical coupling and a 4 × 25.8-Gbps 2-km optical link were demonstrated simultaneously by using a lens-integrated surface-emitting DFB laser (LISEL) array for a low-cost multi-lane optical module. The integrated lens was optimized so that the LISEL had a focused beam, resulting in high-efficiency (−3.5 dB) direct optical coupling to a SMF. Thanks to its short DFB cavity with high-gain InGaAlAs active layer, the LISEL array demonstrated 4 × 25.8-Gbps 2-km error-free transmission. Moreover, it achieved error-free transmission up to 70 °C.

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Many papers have confirmed that the single event vulnerability of semiconductor devices significantly increase with power supply voltage drop, rendering considerable challenges for the radiation harden design as per the development of Moore’s law. The higher the supply voltage of the chip scaling down, the greater severity of these problems. In this article, SET pulse widths induced by heavy ion of T-gate 1.2 V Core and 3.3 V IO devices fabricated by a 130 nm partially depleted silicon-on-insulator technology were directly measured. We discovered that, by adjusting the design parameters and choosing an appropriate device W/L ratio, different power supply voltage SOI devices are able to achieve the same sensitivity for the single event, irrespective of supply voltage. The distribution of SET-pulse widths ranges from 210 to 735 ps under a constant LET of 37.6 MeV-cm²/mg, and the single event transient vulnerability of T-gate 1.2 V Core and 3.3 V IO devices is similar, which is instructive for the low-voltage and low-power circuit application.

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A novel feeding way for balanced feed antennas is presented. To construct the balanced feed antenna, a cross shape loop/spiral antenna (CSA)—a CP antenna invented by the author—needs to be fed through a well-balanced port. A poor current balance will bring a serious deterioration in CP radiation. In addition, the current balance of general ports is not adequate. For these reasons, a feeder reducing the influence of an unbalanced current should be suggested. In this paper, a dipole is employed as a feeder for CSA. S₁₁ characteristics and CP radiation patterns obtained by being fed through a coaxial cable (an unbalanced feed) are compared with those obtained by being fed through a balanced port to discuss the effectiveness of the dipole feeder.

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An improved controller for minimum dc-link-voltage control is proposed. due to its adaptive minimum dc-link voltage characteristic, it can obtain the better compensation performances, and also the minimum dc-link voltage control with self-charging process can be obtained as well as providing the dynamic harmonic currents, it has better dynamic and static characteristics. In order to make an accurate design of the proportional and integral gains, the design procedures of the improved minimum dc-link voltage controller are discussed in detail. Finally, representative simulation and experimental results in a three-phase four-wire center-split shunt APF are presented to verify the validity and effectiveness.

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Conventional microcontroller (MCU)-based devices provide fixed services by executing statically compiled software in on-chip flash memory. In this paper, a newly designed on-demand remote code execution layer of the microcontroller bus architecture is proposed that enables seamless execution of the accessed instructions, which are dynamically loaded from the cloud side in the runtime. The proposed concept is applied to commercial MCUs based on ARM Cortex-M0™, which are implemented using 0.18 um CMOS process with about a 10,000 2-input NAND gates overhead. The experimental results show that the proposed approach results in a 65% reduction of total chip area by eliminating on-chip flash memory, still requiring reasonable code access latency.

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A non-Foster matching network of the receive loop antenna is applied to VLF (very low frequency) band in this paper. Based on an open stable negative impedance converter (NIC) by Linvill, a 1 * 1 m rectangular loop antenna is equivalent as a two-port network, and the non-Foster matching and optimization are realized by a series tunable negative capacitance and negative inductance. The stability of the non-Foster matching network is analyzed and verified also. The results show that compared with the traditional passive matching network from 15 to 30 kHz, by using the non-Foster matching technique, the receive antenna’s input reactance is sufficiently canceled by the negative elements, the −10 dB S₁₁ fractional bandwidth is improved by 64.9%, the total network’s efficiency is improved over most frequency bands.

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The external uncertainties and disturbance affect the DC output of a matrix rectifier (MR) system. This paper presents a sliding mode control (SMC) of uncertain parameters for a MR. Adding a value of anti-voltage into the control function can effectively mitigate the chattering of the sliding motion. Besides, the method of calculating the minimum value of anti-voltage are presented, which can ensure better dynamic performance of a MR. Theoretical and experimental results are presented to verify the correctness and feasibility of the novel control scheme.

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A compact composite open-loop resonator based dual-band band-pass filter (BPF) with high selectivity is presented. The outer open-loop and inner open-loop are corresponding to the first and second frequency passbands, respectively. The middle ring is used as the couping ring. The analysis of these open-loops has also been performed to indicate the resonance condition of the proposed filter. To demonstrate the proposed concept, the filter is fabricated with a compact size, which is 10.20 mm × 18.32 mm. The microstrip line filter is validated and measured with two passbands centered at f₁ = 3.00 GHz and f₂ = 5.34 GHz. The simulation and measured results are in good agreement.

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In this paper, a C-band wideband power amplifier (PA) using a GaN HEMT is proposed. The general Class-J mode, which offer a bigger design space for the fundamental and harmonic terminations, is introduced to implement wideband PA. Then, to verify the mechanism mentioned above, a wideband PA operating from 3.5 to 6.0 GHz is proposed and fabricated. Meanwhile, the load/source harmonic and baseband impedances are also considered for the linearity. The amplifier exhibits 8–11 dB gain and 51%–64% drain efficiency (DE) covering from 3.5 to 5.5 GHz.

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The most useful transmission-line construct is used to realize impedance matching at dual-frequency. The usual algebraic method is to solve the transmission equation which is precise but lack of intuition. A novel graphical method which is simple, intuitive and has explicit physical meaning is proposed to solve the matching problem. The parameters can be determined by simple geometrical relationship. Simulation and experimental results show that the proposed method is convenient, precise and can be used to extend bandwidth as well.

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