This paper proposed a desaturation (DESAT) short circuit (SC) protection circuit for SiC MOSFET, where a blanking time setting module and an SC detection module are designed. The fall time of the drain-source voltage (V_DS) for each switching period of SiC MOSFET is recorded and set as the blanking time for the hard switching fault (HSF) detection in the next switching period. Consequently, the detection delay for HSF is self-adjustive and can respond quickly to the operating state of SiC MOSFET. FPGA and discrete components are used to implement the proposed circuit. The function of the proposed circuit is verified using the double pulse test. The experiment results show that the blanking time automatically increases with the increase of load current. The default detection delay of the proposed protection circuit is set 240ns for HSF and can be adjusted during the subsequent switching period. So in the test under a 400V bus voltage, the detection delay is 240ns for HSF at the first switching period. And for HSF occurs at the second switching period, the detection delay is 200ns adjusted according to the operating state of the first switching period. Meanwhile, the detection delay for fault under load (FUL) is 72ns.

Due to the characteristics of open system and weak signal power of satellite navigation signal, it is very easy to be affected by navigation deception and other interference. At present, most studies divide the influence of deception signal on the receiver into two independent aspects: positioning and timing. There is a lack of research on accurately controlling the positioning and timing of the receiver in the process of deception. In this paper, the principle of accurately controlling positioning and timing in navigation deception are analyzed, three deception scenarios are proposed and verified by experiments. The experiments show that: 1) it is feasible to introduce a step or linear position deviation to the receiver without excessively affecting the timing results; 2) it is feasible to introduce a step or linear time deviation to the receiver without excessively affecting the positioning results: 3) it is feasible to perform position spoofing and time spoofing on the receiver at the same time, the positioning results of the receivers were successfully pulled off by 60m in the experiment, while their timing results were pulled off by 1.5µs.

CMOS power amplifier (PA) has advantages in power consumption and integration, while the lower operating voltage limits its output power. An area efficient power combiner needs to be designed to improve the output power of CMOS PA. An X-band integrated PA using 65-nm CMOS bulk technology was presented in this work. The whole PA consists of two differential stages: a one-way drive amplifier and a two-way main amplifier. By employing a compactly designed high-k output transformer, the CMOS PA occupied a small core-area of 0.47×0.57mm², and delivered 21.6dBm of measured saturated output power with 23.6% of power-added efficiency at 10GHz from a 1.2-V power supply. Simultaneously, this PA can operate well in 8∼15GHz wideband.

A broadband circularly polarized (CP) flower-shaped slot antenna is presented and experimentally studied in this paper. Circular polarization radiation is achieved by a flower-shaped (composed of six ellipses) slot of this antenna. And the irregularly shaped patch with a stub in the center of the slot provides a broad impedance and axial ratio bandwidth. After the prototype is manufactured and tested, it is shown that the measurement results are consistent with the simulation results. The measured results indicate that the proposed antenna has a 3-dB axial ratio bandwidth (ARBW) of 50.7% (from 1.68 to 2.82GHz) at a CP center frequency of 2.2GHz, and a wide -10-dB impedance bandwidth (IBW) of 67.0% (from 1.62 to 3.25GHz). The antenna occupies an overall volume of 0.28λ_l×0.28λ_l×0.005λ_l (λ_l is the free-space wavelength at f_l, f_l=1.68GHz). And the gain values fluctuate slightly within 1.68 to 2.82GHz, and the variation is less than 0.5dBic. In particular, the gain at low frequencies is outstanding compared with similar antennas.

Active power factor correction (PFC) technique is effectively used to improve the power factor and reduce the power exchanging loss, which behaves as a PWM-controlled emulated resistance to the ac power line. The boost topology and its derivatives are commonly applied for PFC stage. In this letter, from a topological point of view, an improved inverse Watkins-Johnson (IWJ) topology-based PFC stage is proposed, which holds several merits including ease of driving, synchronous mode, high efficiency, extra control dimension, and so forth. Theoretical analysis is conducted and an experimental prototype has been constructed to prove the feasibility of the proposed concept.