We propose a novel pulse-swallow programmable frequency divider with a D flip-flop for retiming. The proposed scheme reduces the critical delay path of the modulus control (MC) signal extending the MC timing margin. This enables the high-speed operation of the divider. Moreover, unlike the conventional retiming structure, the MC signal is set and reset by a single signal triggered reset circuitry to eliminate the unwanted division ratio offset and the possible malfunction of set-reset (SR) latch. Simulation results show that the proposed divider designed in 130-nm CMOS technology consumes 53 µW at 1-GHz operation frequency from a 0.7-V supply voltage. The proposed divider achieves the lowest power consumption among the previously reported dividers at GHz operations.

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A switch-back based on charge equalization switching technique for successive-approximation-register (SAR) analog-to-digital converters (ADCs) is proposed. With the proposed switching technique the average switching energy is reduced by 96.86% as compared with the conventional method. This switching scheme can also reduce the total capacitance about 75% with the comparison of the conventional architecture. With the proposed switching scheme the common mode voltage shifts only by 1LSB during all conversion steps, so the dynamic offset of comparator becomes negligible in this case.

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A low phase noise oscillator based on the quarter mode substrate integrated waveguide (QMSIW) technique is presented for the first time. The proposed oscillator is stabilized with the TE₁₀₁ mode of a QMSIW resonator, which is 25% the size of the substrate integrated waveguide (SIW) resonator. In order to obtain a high loaded quality factor, the coupling coefficient between the QMSIW cavity and microstrip is tuned to be undercoupled. A X-band Prototype has been designed and fabricated. By using the QMSIW resonator, the fabricated oscillator has a more compact size than the SIW counterpart. The measured results show that the oscillator has a phase noise of −98.5 dBc/Hz at 100 kHz at 9.03 GHz, and an output power of 5.04 dBm with a DC consumption of 20 mW.

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The speech distortion weighted multi-channel Wiener filter (SDW-MWF) is considered to control the tradeoff between noise reduction and speech distortion. In a single target speech source, speech correlation matrix can be assumed to be rank-1 in the implementation of the SDW-MWF. We evaluate the rank-1 SDW-MWF as a pre-processor of speech recognizer and discuss regarding optimal distortion weight. We also propose a modified SDW-MWF providing a full range control of speech distortion as well as outperforming the rank-1 SDW-MWF. The experimental results show that aggressive noise reduction strategy is preferable for maximizing the performance of speech recognizer. The results also show that the proposed filter performs better than the conventional rank-1 SDW-MWF.

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This paper presents a detailed study of the impact of SEUs in the configuration RAM (CRAM) of SRAM based FPGAs. Since modern SRAM based FPGAs support scrubbing of the CRAM, a new, intermittent CRAM SEU fault model is presented. This fault model is implemented both in simulation and on an emulation platform for an embedded processor design. The criticality of CRAM bits is studied based on their logic function, the duration of the SEU, and the workload running on the processor. These results provide new insight into the overall effectiveness of CRAM scrubbing mechanisms.

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The use of smartphones has increased the opportunity to communicate on trains. Therefore, the penetration loss by the train structure is an important consideration when designing the radio link in a mobile communications system. In this study, we evaluate the penetration loss of UHF band radio waves on a train. First, we analyzed the penetration loss on the train by electromagnetic field simulation. Then, we measured the penetration loss on the train and compared the results to those of the electromagnetic field simulation. The electromagnetic field simulation and measured results were found to be in good agreement.

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A 5–8 GHz internally matched Gallium Nitride (GaN) power amplifier (PA) with 100 W output power was realized in this letter. The theory of load line match was used and extended. Power contour was depicted and revised by the output capacitance of GaN High Electron Mobility Transistor (HEMT). Impedance was matched into the −1 dB power contour in a wide frequency band due to the ladder transmission line matching network and broadband power combiner. With the package size of 14.5 ∗ 14.8 mm, the proposed power amplifier has the maximum output power of 102 W with 45.8% associate power added efficiency (PAE) at the frequency of 6.5 GHz, and output power over 85 W and PAE over 42.8% at the frequency band of 5–8 GHz.

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In this paper, a high-speed low-power 18T CMOS full adder design featuring full-swing output is proposed. The adder is designed and simulated using pass transistor logic of the 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP) of its critical path is 22 × 10⁻¹⁸ J, which is a marked improvement of 61% to 98% compared against those of the 28T conventional CMOS, 20T transmission gate (TGA), 16T transmission function (TFA), 14T hybrid, 24T hybrid pass logic with static CMOS, and 28T differential pass logic (DPL) full adders simulated with the same process technology. Its power consumption is lower by 32% to 85%, with speed performance comparable to those of other high-speed adders reported in the literature. Occupying an aerial footprint of only 107 µm² (8.00 µm × 13.41 µm), the proposed full adder is also capable to function at lower supply voltages of 0.4 V and 0.8 V without significant performance degradation.

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A novel design of filter based on substrate integrated waveguide (SIW) structure is presented in this letter, and a pair of broadside-coupled complementary split ring resonators (BC-CSRRs) are used in the filter. The filter has a very simple structure and a very compact size. Its characteristics are discussed. In order to verify the proposed design, an example of the proposed filter with a center frequency of 5 GHz is fabricated and measured, and good results obtained. Moreover, a way to make further use of the proposed structure to design dual-band filter is also discussed in this letter, and an example of dual-band filter has been fabricated and measured.

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A three-dimensional (3-D) QCA architecture is proposed in this express. The design of a 3-D quantum-dot cellular automata (QCA) full adder based on 3-D inverters and majority gates is presented and compared with its 2-D counterparts. The 3-D adder uses over 46% less cells and occupies 40% less area compared with the best 2-D design. The proposed 3-D QCA architecture offers an additional dimension for computation, which is not available in current CMOS technology.

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