This letter proposes a parasitic elimination bootstrapped switch and a fast settling residual amplifier to be used in multiplying digital-to-analog converter (MDAC) in order to improve the performance of pipelined ADC at high frequency. The parasitic elimination bootstrapped switch improves the sampling spurious free dynamic range (SFDR) by more than 6dB by shielding the nonlinear parasitic capacitance of the MOS transistor substrate. In addition, at high frequency, the negative zero point introduced by the later stage switch-capacitor circuit (which is easy to be ignored) will seriously deteriorates the settling time of residual amplifier in the former stage. A new zero-pole elimination technique is proposed, which greatly reduces the settling time of residual amplifier by nearly 11% and further improve the performance of MDAC. Simulated in 28nm CMOS technology, as the input signal is 1.38GHz, the former stage of the pipelined ADC implements high-speed high-resolution to obtain a SFDR of 75.77dB and a signal-to-noise-plus-distortion ratio (SNDR) of 68.05dB at a sampling frequency of 2.2GS/s.

The transient response characteristics such as overshoot and undershoot can be affected by the external capacitors of the LDO regulator. However, the capacitor-less LDO regulator proposed in this paper has an SR-Latch switch structure applied to the output terminal and gate terminal of the pass transistor in order to achieve improved transient response and secure excellent current driving capability. In addition, the proposed ESD protection device uses Penta-Well in low voltage applications embedded in the output stage and power line based on SCR (Silicon Control Rectifier) to provide improved ESD robustness characteristics. As a result, the transient response characteristics of the proposed LDO regulator with the SR-Latch switch structure were improved and the quiescent current was secured. The operating conditions of the proposed LDO regulator with the SR-Latch switch structure were set to an input voltage of 3.3V to 4.5V, maximum load current of 250mA, and an output voltage of 3V. As a result of the measurement, it was confirmed that the proposed LDO regulator maintained an undershoot voltage of 42mV and an overshoot voltage of 31mV when a load current of 250mA was applied. In addition, HBM ESD robustness is guaranteed at 6kV.

In the ultra-high speed four-level pulse amplitude modulation (PAM4) optical receiver, the data phase jitter is deteriorated by inter-symbol interference (ISI), level transitions and sampling clock. This paper analyzed in detail the causes of phase jitter, and then proposed a novel PAM4 clock and data recovery (CDR) architecture. A three-lane quarter-rate phase detector with majority voter was employed to suppress the input phase jitter caused by discrete zero-crossings, and an optimized quadrature voltage-controlled oscillator (QVCO) was designed to provide stable and precise sampling clock. The PAM4 CDR was optimally designed based on IHP 0.13µm SiGe BiCMOS process, and the post-simulation results indicates that our CDR can operate properly at 100Gb/s with a peak-to-peak jitter of 5.52ps.