The Wuhan Ionospheric Sounding System (WISS), based on FPGA and DDS architecture with USB communication, was developed for studying the ionosphere by the Ionospheric Laboratory of Wuhan University. This letter presents an improved hardware system of WISS, which is based on network port communication and suitable for software defined radio. The output waveforms are more controllable and more diversified in the improved system than the previous version. The new version of ionospheric sounding system can not only conduct conventional ionospheric exploration, but also implement meteors sounding by VHF band. The system structure and the design scheme of each module are described in detail. Then, some typical experiment results are carried out to verify the performance of the improved system. Results show that the new version system performed well in the experiments of ionospheric meteors sounding.

Defect pattern detection of wafer bin maps (WBMs) is vital in wafer quality improvement owing to preventing further defects and resource waste. We proposed two Mixup approaches to train Vision Transformer under only single defect WBM samples for mixed-type defects recognition. We use UnionMixup and Token level Max-Min-Saliency Mixup to generate mixed-type defect WBMs to feed Vision Transformers. In the recognition of two-mixed defect types WBMs, our method improves 17.1% compared to baseline (none mixup) and we have 1.7% accuracy gain compared with state-of-the-art mixup approaches. In the recognition mixed defect samples containing more than two-mixed defects (three-mixed and four-mixed), we gain at least 24.7% (compared with baseline) and 11.1% (compared with single SOTA mixup) respectively. The combination of Union Mixup and Token level Max-Min-Saliency Mixup become better than other SOTA mixup methods obviously in mixed patterns including more than three defects.

To improve the tracking processing speed of embedded Global Navigation Satellite System (GNSS) receivers, we propose seven custom instructions and a tracking accelerator integrated into the self-developed 32-bit RISC-V processor named Prism. The accelerator can increase execution speed significantly at a reasonable area and power cost. The FPGA test and synthesis under the 40nm technology showed that the accelerator achieved 58% to 94% speed increase for three tracking loops, and 122% to 700% speed increase for seven custom instructions, at the cost of 33.1% more area and 19.8% more power consumption.

This article presents a high-linear phase-locked-loop-based (PLL-based) frequency-modulated continuous-wave (FMCW) frequency synthesizer for 77GHz automotive radar applications. A behavioral model of the rms FM error by constructing the PLL transient response under a unit frequency step and taking into account the slope of the chirp signal is developed. Simulation results demonstrate the effectiveness of the proposed model in optimizing chirp linearity. The behavioral model is used to facilitate the design of the 77GHz FMCW synthesizer fabricated in a 55nm CMOS process. A gain linearized varactor approach is also developed to linearize the voltage-controlled oscillator (VCO) gain (K_VCO) to ensure constant PLL bandwidth maintaining optimum chirp linearity. Measurement results show that the synthesizer achieves a 1.2GHz chirp bandwidth, a minimum rms FM error of 42kHz (0.0035% of the chirp bandwidth) under a 4.219MHz/µs chirp slope while consuming 74.6mW of power. The measured integer-N mode and fractional-N mode phase noises normalized to 78GHz are -81.6dBc/Hz and -80.1dBc/Hz at 1MHz offset, respectively.

A modified dual-transformer topology with associated analysis is presented in this paper, which maintained soft-switching operation and depressed current stress to achieve higher conversion efficiency. The proposed resonant converter it contained two transformers and adopted phase shift modulation to regulate output power, so that converters output power can be controlled in simple and stable strategy. A method to depress resonant current stress is proposed in design progress. With lower current and fewer power components is helpful to reduce conduction loss. Based on the steady-state analysis, a design example is given. Finally, experimental works and comparison work on a lab prototype are performed, which validate the performance improvement of the proposed converter.

This paper presents an electronic readout system based on the resistance anode, which is capable of processing the output signal from the resistance anode. This design divides the electronic readout circuit into two parts: analog circuit design and digital circuit design. The analog pre-processing circuit the electric charge signal from the resistive anode detector into a voltage signal and amplifies it and the digital part consists of a trapezoidal double-channel shaping algorithm implemented in FPGA. This design overcomes pulse pile-up at high count rates.

Reverse engineering has been a serious threat to integrated circuit hardware security, and gate camouflaging is effective to resist it. Existing camouflage techniques often require process change or rely on emerging devices, and they generally come with significant costs and overhead. In this paper, we propose a novel dynamic camouflage technique based on crosstalk, and used dynamic CMOS to design three camouflaged gates: BUF, AND, and OR. Our technique transmits signal without physical connections, which not only obfuscates the functionality of the logic gates but also conceal the real source of the signal. Moreover, it does not require any process changes. Simulation results show the average area, delay and power overhead is 3.07X, 1.75X and 0.8X respectively comparing to standard dynamic gates. The proposed technique also operates reliably under various Process, Voltage, and Temperature (PVT) conditions.

This work presents a neural network DPD for mmWave RF-PAs. Differently from existing neural network-based DPDs, the neural network in the proposed DPD does not reside in the forward data path. Instead, it estimates the polynomial coefficients from the complex Fourier amplitudes of harmonics during a calibration sweep. It can compensate for PA nonlinearity under various operating conditions with lower hardware complexity compared to conventional DPDs. The proposed design is validated on a 28GHz CMOS phased-array transceiver. In 256-QAM 5G-OFDMA-mode, the proposed neural network DPD achieved an improvement in EVM from -28.7dB to -32.0dB, while maintaining an ACLR of -33.4dBc.

A monolithic wavelength selective switch (WSS) using a silicon waveguide was fabricated and its characteristics were measured. The crosstalk of the silicon arrayed-waveguide grating (AWG) is reduced by introducing a Bragg grating filter (BGF), which can realize a waveguide type WSS with both fast switching and low crosstalk performance. The extinction ratio of the BGF was approximately 20dB with a 3-dB bandwidth of 0.6nm. The AWG had an average loss of 9.5dB with a large second peak crosstalk. Switching experiments showed that the total loss averaged 20.5dB, the crosstalk averaged -13.9dB, and that switching responses were 13µs for both the rise and fall.

The effect of internal radial stress generated during the annealing process on the mobility of through-silicon via (TSV) vertical switch are analyzed in detail, by employing finite element software ANSYS and orthogonal experimental design method. The results show that, the TSV diameter has the largest effect on the mobility of the TSV vertical switch, while the equilateral triangle array produces the smallest effect of stress at the same distance.