IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
E100.C 巻, 11 号
選択された号の論文の25件中1~25を表示しています
Special Section on Electronic Displays
Regular Section
  • Rui JI, Jinchun GAO, Gang XIE, Qiuyan JIN
    原稿種別: PAPER
    専門分野: Electromechanical Devices and Components
    2017 年E100.C 巻11 号 p. 1052-1060
    発行日: 2017/11/01
    公開日: 2017/11/01
    ジャーナル 認証あり

    Coaxial connectors are extensively used in electrical systems and the degradation of the connector can alter the signal that is being transmitted and leads to faults, which is one of the major causes of low communication quality. In this work, the failure features caused by the degraded connector contact surface were studied. The relationship between the DC resistance and decreased real contact areas was given. Considering the inductance properties and capacitive coupling at high frequencies, the impedance characteristics of the degraded connector were discussed. Based on the transmission line theory and experimental measurement, an equivalent lump circuit of the coaxial connector was developed. For the degraded contact surface, the capacitance was analyzed, and the frequency effect was investigated. According to the high frequency characteristics of the degraded connector, a fault detection and location method for coaxial connectors in RF system was developed using a neural network method. For connectors suffering from different levels of pollution, their impedance modulus varies continuously. Considering the range of the connector's impedance parameters, the fault modes were determined. Based on the scattering parameter simulation of a RF receiver front-end circuit, the S11 and S21 parameters were obtained as feature parameters and Monte Carlo simulations were conducted to generate training and testing samples. Based on the BP neural network algorithm, the fault modes were classified and the results show the diagnosis accuracy was 97.33%.

  • Nobutaro SHIBATA, Mayumi WATANABE, Takako ISHIHARA
    原稿種別: PAPER
    専門分野: Integrated Electronics
    2017 年E100.C 巻11 号 p. 1061-1068
    発行日: 2017/11/01
    公開日: 2017/11/01
    ジャーナル 認証あり

    Multiport SRAMs are frequently installed in network and/or telecommunication VLSIs to implement smart functions. This paper presents a high speed and low-power dual-port (i.e., 1W+1R two-port) SRAM macro customized for serial access operations. To reduce the wasted power dissipation due to subthreshold leakage currents, the supply voltage for 10T memory cells is lowered to 1 V and a power switch is prepared for every 64 word drivers. The switch is activated with look-ahead decoder-segment activation logic, so there is no penalty when selecting a wordline. The data I/O circuitry with a new column-based configuration makes it possible to hide the bitline precharge operation with the sensing operation in the read cycle ahead of it; that is, we have successfully reduced the read latency by a half clock cycle, resulting in a pure two-stage pipeline. The SRAM macro installed in a 4K-entry × 33-bit FIFO memory, fabricated with a 0.3-µm fully-depleted-SOI CMOS process, achieved a 500-MHz operation in the typical conditions of 2- and 1-V power supplies, and 25°C. The power consumption during the standby time was less than 1.0 mW, and that at a practical operating frequency of 400 MHz was in a range of 47-57 mW, depending on the bit-stream data pattern.

  • Ki-Seung LEE
    原稿種別: BRIEF PAPER
    専門分野: Optoelectronics
    2017 年E100.C 巻11 号 p. 1069-1072
    発行日: 2017/11/01
    公開日: 2017/11/01
    ジャーナル 認証あり

    In photoacoustic imaging, laser power variation is one of the major factors in the degradation of the quality of reproduced images. A simple, but efficient method of compensating for the variations in laser pulse energy is proposed here where the characteristics of the adopted optical sensor and acoustic sensor were estimated in order to minimize the average local variation in optically homogeneous regions. Phantom experiments were carried out to validate the effectiveness of the proposed method.

  • Jaeyong CHUNG, Woochul KANG
    原稿種別: BRIEF PAPER
    専門分野: Integrated Electronics
    2017 年E100.C 巻11 号 p. 1073-1076
    発行日: 2017/11/01
    公開日: 2017/11/01
    ジャーナル 認証あり

    Massive amounts of computation involved in real-time evaluation of deep neural networks pose a serious challenge in battery-powered systems, and neuromorphic systems specialized in neural networks have been developed. This paper first shows the portion of active neurons at a time dwindles as going toward the output layer in recent large-scale deep convolutional neural networks. Spike-based, asynchronous neuromorphic systems take advantage of the sparse activation and reduce dynamic power consumption, while synchronous systems may waste much dynamic power even for the sparse activation due to clocks. We thus propose a clock gating-based dynamic power reduction method that exploits the sparse activation for synchronous neuromorphic systems. We apply the proposed method to a building block of a recently proposed synchronous neuromorphic computing system and demonstrate up to 79% dynamic power saving at a negligible overhead.

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