SoC has driven the evolution of embedded systems or consumer electronics. Multi-core/multi-IP is the key technology to integrate many functions on a SoC for future embedded applications. In this paper, the transition of SoC and its required functions for cellular phones as an example is described. And the state-of-the-art multi-core technology of homogeneous type and heterogeneous type are shown. When many cores and IPs are integrated on a chip, collaboration between cores and IPs becomes important to meet requirement. To realize it, “MPSoC Platform” concept and elementary technology for this platform is described.

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This paper describes the architecture of an integrated platform developed for improving the development efficiency of system LSIs built into digital consumer electronics equipment such as flat-panel TVs and optical disc recorders. The reason for developing an integrated platform is to improve the development efficiency of system LSIs that serve the principal functions of the said equipment. The key is to build a common interface between each software layer, with the system LSI located at the lowest layer. To make this possible, the hardware architecture of the system LSI is divided into five blocks according to its main functionality. In addition, a middleware layer is placed over the operating system to improve the ease of porting old applications and developing new applications in the higher layer. Based on this platform, a system LSI called UniPhier™ has been developed and used in 156 product families of digital consumer electronics equipment (as of December 2008).

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This paper presents a gate-block selection algorithm, which can synthesize a proper parameter extractor of the pre-computation-based content-addressable memory (PB-CAM) to enhance power efficiency for specific applications such as embedded systems, microprocessor and SOC, etc. Furthermore, a novel CAM cell design with single bit-line is proposed. The proposed CAM cell design requires only one heavy loading bit-line and merely is constructed with eight transistors. The whole PB-CAM design was described in Spice with TSMC 0.35µm double-poly quadruple-metal CMOS process. We used Synopsys Nanosim to estimate power consumption. With a 128 words by 32bits CAM size, the experimental results showed that our proposed PB-CAM effectively reduces 18.21% of comparison operations in the CAM and saves 16.75% in power reduction by synthesizing a proper parameter extractor of the PB-CAM compared with the 1's count PB-CAM. This implies that our proposed PB-CAM is more flexible and adaptive for specific applications.

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A novel 300MHz embedded flash memory for dual-core microcontrollers with a shared ROM architecture is proposed. One of its features is a three-stage pipeline read operation, which enables reduced access pitch and therefore reduces performance penalty due to conflict of shared ROM accesses. Another feature is a highly sensitive sense amplifier that achieves efficient pipeline operation with two-cycle latency one-cycle pitch as a result of a shortened sense time of 0.63ns. The combination of the pipeline architecture and proposed sense amplifiers significantly reduces access-conflict penalties with shared ROM and enhances performance of 32-bit RISC dual-core microcontrollers by 30%.

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Despite the prevalence of Java workloads across a variety of processor architectures, there is very little published data on the impact of the various processor design decisions on Java performance. We attribute the lack of data to the large design space resulting from the complexity of the modern superscalar processor and the additional complexities associated with executing Java bytecode using a virtual machine. To address this shortcoming, we use a statistically rigorous methodology to systematically quantify the the impact of the various processor microarchitecture parameters on Java execution performance. The adopted methodology enables efficient screening of significant factor effects in a large design space consisting of 35 factors (32-billion potential configurations) using merely 72 observations per benchmark application. We quantify and tabulate the significance of each of the 35 factors for 13 benchmark applications. While these tables provide various insights into Java performance, they consistently highlight the performance significance of the instruction delivery mechanism, especially the instruction cache and the ITLB design parameters. Furthermore, these tables enable the architect to identify processor bottlenecks for Java workloads by providing an estimate of the relative impact of various design decisions.

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Credit-based router-to-router flow control is one main link-level flow control mechanism proposed for Networks on Chip (NoCs). Based on network calculus, we analyze its performance and optimal buffer size. To model the feedback control behavior due to credits, we introduce a virtual network service element called flow controller. Then we derive its service curve, and further the system service curve. In addition, we give and prove a theorem that determines the optimal buffer size guaranteeing the maximum system service curve. Moreover, assuming the latency-rate server model for routers, we give closed-form formulas to calculate the flit delay bound and optimal buffer size. Our experiments with real on-chip traffic traces validate that our analysis is correct; delay bounds are tight and the optimal buffer size is exact.

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Compiler is the most important supporting tool to facilitate the use of reconfigurable computing architecture (RCA). In this paper, a template-based compiler framework is proposed. This compiler can synthesize the executables for RCA from native high-level programming language source code directly. It supports to generate run-time dynamic configuration context. And it is capable to generate both full configuration context and partial configuration context. Experimental results show that the executables generated by the proposed compiler can achieve better execution performance and smaller configuration context size than previous compilers. Moreover, this compiler does not require the programmer to have any extra knowledge about the hardware architecture of RCA.

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A low-power K-band CMOS current-mode up-conversion mixer is proposed. The proposed mixer is realized using four analog current-squaring circuits. This current-mode up-conversion mixer is fabricated in 0.13-µm 1P8M triple-well CMOS process, and has the measured power conversion gain of -5dB. The fabricated CMOS up-conversion mixer dissipates only 3.1mW from a 1-V supply voltage. The VCO can be tuned from 20.8GHz to 22.7GHz. Its phase noise is -108dBc/Hz at 10-MHz offset frequency. It is shown that the proposed mixer has great potential for low-voltage and low-power CMOS transmitter front-ends in advanced nano-CMOS technologies.

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A new on-chip current sensing circuit suitable for step-down switch-mode power converters (SMPC) is presented in this paper. It can be used in a high speed SMPC. The sense voltage is quite accurate and temperature independent. The structure is very simple. Only eight transistors and a sensing resistor are used. This current sensing technique has been fabricated with a standard 0.5µm DPDM CMOS process. Experimental results show that the proposed circuit can work well in DC-DC converters such that the loading current can be managed through control theories.

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This paper describes the architecture and implementations of an automatic digital tuning circuit for a complex bandpass filter (BPF) in a low-power and low-cost transceiver for applications such as personal authentication and wireless sensor network systems. The architectural design analysis demonstrates that an active RC filter in a low-IF architecture can be at least 47.7% smaller in area than a conventional g_m-C filter; in addition, it features a simple implementation of an associated tuning circuit. The principle of simultaneous tuning of both the center frequency and bandwidth through calibration of a capacitor array is illustrated as based on an analysis of filter characteristics, and a scalable automatic digital tuning circuit with simple analog blocks and control logic having only 835 gates is introduced. The developed capacitor tuning technique can achieve a tuning error of less than ±3.5% and lower a peaking in the passband filter characteristics. An experimental complex BPF using 0.18µm CMOS technology can successfully reduce the tuning error from an initial value of -20% to less than ±2.5% after tuning. The filter block dimensions are 1.22mm × 1.01mm; and in measurement results of the developed complex BPF with the automatic digital tuning circuit, current consumption is 705µA and the image rejection ratio is 40.3dB. Complete evaluation of the BPF indicates that this technique can be applied to low-power, low-cost transceivers.

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This Paper presents the design of a wideband variable gain amplifier (VGA) using 0.18µm standard CMOS technology. The proposed VGA realizes wideband flat gain using wideband flat negative capacitance. It achieves a 3dB gain bandwidth of 1GHz with a maximum gain of 23dB. Also, it shows P1dB of -33 to -6dBm over the gain range of -28 to 23dB. The overall current consumption is 5.5mA under a 1.5V supply.

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A new delay-locked loop (DLL)-based multiphase generator is presented. To achieve an arbitrary integer multiplication factor, a voltage-controlled variable delay ring (VCDR) is adopted, and a new “generate and reset” (GNR) cell is developed. The whole circuit of the closed loop was designed and characterized in a 1.2-V 0.13-µm CMOS process. The simulated results show that the loop operates from 1.0MHz to 1.2GHz under the supply voltage of 1.2V, and the GNR cell exhibits low supply sensitivity of 1300-ps/V.

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In this paper, first the temperature distribution of the pyramidal EM-wave absorber is calculated in the coupled method. Next, the injected power to the EM-wave absorber is changed to estimate the maximum power density that the EM-wave absorber can resist. As a result, the limitation of the injecting power density to a pyramidal EM-wave absorber is achievable.

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This letter presents the construction and design equations of a lumped element Wilkinson divider with dual-band operation. This divider is constructed of series and parallel LC resonant circuits, and an isolation resistor. The element values can be uniquely determined by giving the two frequencies for operation as a Wilkinson divider and the load resistance. An 800MHz/2GHz dual-band Wilkinson divider is treated as a design example, and its operation is verified by simulation and experiment. The fabricated divider has compact dimensions of 3.56 × 4mm².

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This letter proposes a new hybrid EM wave absorber with the crossed-wedge shape, which can be applied to 3m semi anechoic chambers. In this study, we designed a new hybrid EM wave absorber with the crossed-wedge shape, which consisted of the inorganic and organic thin corrugated dielectric lossy sheet containing organic conductive fibers. Then the 3m semi anechoic chamber is constructed in the size of 9.0m × 6.0m × 5.7m (L × W × H) using these absorbers, and also the normalized site attenuation (NSA) is measured according to ANSI C63.4 in the frequency range of 30MHz to 1GHz. As a result, the measured NSA is obtained within ±3dB of the theoretical one.

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A novel low-power kick-back reduced comparator for use in high-speed flash analog-to-digital converters (ADC) is presented. The proposed comparator combines cascode transistors to reduce the kick-back noise with a built-in threshold voltage to remove the static power consumption of a reference. Without degrading other figures, the kick-back noise is reduced by a factor 8, compared to a previous design without cascode transistors. An improved calibration structure is also proposed to improve linearity when used in an ADC. Simulated in a standard CMOS technology the comparator consumes 106.5µW at 1.8V power supply and 1GHz clock frequency.

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