Ferroelectric gate field-effect transistors (MFSFETs) were investigated utilizing nondoped HfO₂ deposited by RF magnetron sputtering utilizing Hf target. After the post-metallization annealing (PMA) process with Pt top gate at 500^°C/30s, ferroelectric characteristic of 10nm thick nondoped HfO₂ was obtained. The fabricated MFSFETs showed the memory window of 1.7V when the voltage sweep range was from -3 to 3V.

In this paper, the effects of the TiN encapsulating layer and the dopant segregation process on the interface properties and the Schottky barrier height reduction of PdEr-silicide/n-Si(100) were investigated. The results show that controlling the initial location of the boron dopants by adding the TiN encapsulating layer lowered the Schottky barrier height (SBH) for hole to 0.20 eV. Furthermore, the density of interface states (D_it) on the order of 10¹¹eV^-1cm^-2 was obtained indicating that the dopant segregation process with TiN encapsulating layer effectively annihilated the interface states.

In this paper, the influence of high-temperature sputtering on the nitrogen-doped (N-doped) LaB₆ thin film formation utilizing RF sputtering was investigated. The N-doped LaB₆/SiO₂/p-Si(100) MOS diode and N-doped LaB₆/p-Si(100) of Schottky diode were fabricated. A 30 nm thick N-doped LaB₆ thin film was deposited from room temperature (RT) to 150^°C. It was found that the resistivity was decreased from 1.5 mΩcm to 0.8 mΩcm by increasing deposition temperature from RT to 150^°C. The variation of work function was significantly decreased in case that N-doped LaB₆ thin film deposited at 150^°C. Furthermore, Schottky characteristic was observed by increasing deposition temperature to 150^°C. In addition, the crystallinity of N-doped LaB₆ thin film was improved by increasing deposition temperature.

We have investigated the in-situ N₂-plasma nitridation for high-k HfN gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering to improve the electrical characteristics. It was found that the increase of nitridation gas pressure for the deposited HfN_1.1 gate insulator, such as 98 mPa, decreased both the hysteresis width in C-V characteristics and leakage current. Furthermore, the 2-step nitiridation process with the nitridation gas pressure of 26 mPa followed by the nitridation at 98 mPa realized the decrease of equivalent oxide thickness (EOT) to 0.9 nm with decreasing the hysteresis width and leakage current. The fabricated metal-insulator-semiconductor field-effect transistor (MISFET) with 2-step nitridation showed a steep subthreshold swing of 87 mV/dec.

In this study, simulations are performed to design an optimal device for thinning the GaN channel layer on the semi-insulating layer in HEMT. When the gate length is 50nm, the thickness of the undoped channel must be thinner than 300nm to observe the off state. When the GaN channel layer is an Fe-doped, an on/off ratio of ~300 can be achieved even with a gate length of 25nm, although the transconductance is slightly reduced.

This paper presents the feasibility of a capacitive coupler utilizing an electric double layer for wireless power transfer under seawater. Since seawater is an electrolyte solution, an electric double layer (EDL) is formed on the electrode surface of the coupler in direct current. If the EDL can be utilized in radio frequency, it is possible that high power transfer efficiency can be achieved under seawater because a high Q-factor can be obtained. To clarify this, the following steps need taking; First, measure the frequency characteristics of the complex permittivity in seawater and elucidate the behaviors of the EDL from the results. Second, clarify that EDL leads to an improvement in the Q-factor of seawater. It will be shown in this paper that capacitive coupling by EDL occurs using two kinds of the coupler models. Third, design a coupler with high efficiency as measured by the Q-factor and relative permittivity of EDL. Last, demonstrate that the designed coupler under seawater can achieve over 85% efficiency at a transfer distance of 5 mm and feasibility of the coupler with EDL.

A method for estimating circuit performance variation caused by packaging-induced mechanical stress is proposed. The developed method is based on the stress distribution chart for the target integrated circuit (IC) and the stress sensitivity characteristics of individual devices. This information is experimentally obtained using a specially designed test chip and a cantilever bending calibration system. A post-packaging analysis and simulation tool, called Stress Netlist Generator (SNG), is developed for conducting the proposed method. Based on the stress distribution chart and the stress sensitivity characteristics, SNG modifies the SPICE model parameters in the target netlist according to the impact of the packaging-induced stress. The netlist generated by SNG is used to estimate packaging-induced performance variation with high accuracy. The developed method is remarkably effective even for small-scale ICs with chip sizes of roughly 1 mm², such as power management ICs, which require higher precision.

A laser imaging detection and ranging (LIDAR) is one of the key sensors for autonomous driving. In order to improve its performance of the measurable distance, especially toward the front-side direction of the vehicle, this paper presents rapid revolution speed control of a brushless DC (BLDC) motor with a cyclostationary command signal. This enables the increase of the signal integration time for the designated direction, and thus improves the signal-to-noise ratio (SNR), while maintaining the averaged revolution speed. We propose the use of pre-emphasis circuits to accelerate and decelerate the revolution speed of the motor rapidly, by modifying the command signal so as to enhance the transition of the speed. The adaptive signal processing can adjust coefficients of the pre-emphasis filter automatically, so that it can compensate for the decayed response of the motor and its controller. Experiments with a 20-W BLDC motor prove that the proposed technique can achieve the actual revolution speed output to track the designated speed profile ranging from 600 to 1400 revolutions per minute (rpm) during one turn.

In this paper, an enhanced well-changed GGNMOS (EW-GGNMOS) is proposed and demonstrated. The new device has the same topology as the conventional 3.3V GGNMOS, except that its well has been changed to the 1.2V p-well. Attributed to higher doping concentration, resulting in a much lower trigger voltage and desirable turn-on uniformity compared to conventional 3.3V GGNMOS. Therefore, we can use EW-GGNMOS as a 3.3V ESD protection device without any additional process.