IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
E94.C 巻, 11 号
選択された号の論文の18件中1~18を表示しています
Special Section on Electronic Displays
Regular Section
  • Mitsutoshi MORINAGA, Toshiyuki NAGASAKU, Hiroshi SHINODA, Hiroshi KOND ...
    原稿種別: PAPER
    専門分野: Microwaves, Millimeter-Waves
    2011 年 E94.C 巻 11 号 p. 1773-1778
    発行日: 2011/11/01
    公開日: 2011/11/01
    ジャーナル 認証あり
    A 24-GHz continuous wave (CW) radar with three vertically switched beam antennas for monitoring different range segments has been newly proposed and developed as a means to detect intruders in a fan-shaped ground area with 90degs. in azimuth and over 10m in range. This radar can detect moving targets and measure their positions from a tampering-proof height of about 5m by taking advantage of a two-frequency-CW modulation technique and monopulse scheme used to achieve the wide azimuth coverage. The radar module consists of microstrip-patch planar antennas and monolithic microwave integrated circuits (MMICs), which are placed on the opposite side of a single metal plate to attain compact size and lower cost. An experimental radar successfully detected a human intruder with a position accuracy of 50cm when moving at 1.4m/s.
  • Tae-Ho KIM, Yong-Hwan MOON, Jin-Ku KANG
    原稿種別: PAPER
    専門分野: Electronic Circuits
    2011 年 E94.C 巻 11 号 p. 1779-1786
    発行日: 2011/11/01
    公開日: 2011/11/01
    ジャーナル 認証あり
    This paper presents an adaptive FFE/DFE receiver with an algorithm that measures the data-dependent jitter. The proposed adaptive algorithm determines the compensation level by measuring the input data-dependent jitter. The adaptive algorithm is combined with a clock and data recovery phase detector. The receiver is fabricated in with 0.13µm CMOS technology, and the compensation range of equalization is up to 26dB at 2GHz. The test chip is verified for a 40 inch FR4 trace and a 53cm flexible printed circuit channel. The receiver occupies an area of 440µm × 520µm and has a power dissipation of 49mW (excluding the I/O buffers) from a 1.2V supply.
  • Bongsub SONG, Kwangsoo KIM, Jinwook BURM
    原稿種別: PAPER
    専門分野: Electronic Circuits
    2011 年 E94.C 巻 11 号 p. 1787-1793
    発行日: 2011/11/01
    公開日: 2011/11/01
    ジャーナル 認証あり
    A 12Gb/s 10-level pulse amplitude modulation (PAM) serial-link transmitter was implemented using a 0.18µm CMOS process. The proposed 10-PAM transmitter achieves a channel efficiency of 4bit/symbol by dual-mode amplitude modulations using 10 differential-mode levels and 3 common-mode levels. The measured maximum data-rate was 12Gb/s over 0.7-m cable and 2-cm printed circuit board (PCB) traces. The entire transmitter consumes 432mW such that the figure of merit of the transmitter is 36pJ/bit. The present work demonstrates the greater channel efficiency of 4bit/symbol than the currently reported multi-level PAM transmitters.
  • Yoshihiro KOKUBO
    原稿種別: BRIEF PAPER
    専門分野: Microwaves, Millimeter-Waves
    2011 年 E94.C 巻 11 号 p. 1794-1797
    発行日: 2011/11/01
    公開日: 2011/11/01
    ジャーナル 認証あり
    Dielectric rod arrays in a metallic waveguide alter the propagation modes and group velocities of electromagnetic waves. We have focused on TE30-to-TE10 mode converters and investigated how their behavior varies with frequency. A mode converter is proposed that passes the TE10 mode at frequencies lower than 2ƒc, and converts the TE30 mode into the TE10 mode for frequencies higher than 3ƒc.
  • Ji-Hun EO, Sang-Hun KIM, Young-Chan JANG
    原稿種別: BRIEF PAPER
    専門分野: Electronic Circuits
    2011 年 E94.C 巻 11 号 p. 1798-1801
    発行日: 2011/11/01
    公開日: 2011/11/01
    ジャーナル 認証あり
    A 200kS/s 10-bit successive approximation (SA) analog-to-digital converter (ADC) with a rail-to-rail input signal is proposed for acquiring biosignals such as EEG and MEG signals. A split-capacitor-based digital-to-analog converter (SC-DAC) is used to reduce the power consumption and chip area. The SC-DAC's linearity is improved by using dummy capacitors and a small bootstrapped analog switch with a constant on-resistance, without increasing its area. A time-domain comparator with a replica circuit for clock feed-through noise compensation is designed by using a highly differential digital architecture involving a small area. Its area is about 50% less than that of a conventional time-domain comparator. The proposed SA ADC is implemented by using a 0.18-µm 1-poly 6-metal CMOS process with a 1V supply. The measured DNL and INL are +0.44/-0.4 LSB and +0.71/-0.62 LSB, respectively. The SNDR is 55.43dB for a 99.01kHz analog input signal at a sampling rate of 200kS/s. The power consumption and core area are 5µW and 0.126mm2, respectively. The FoM is 47fJ/conversion-step.
  • Yuanwang YANG, Jingye CAI, Haiyan JIN
    原稿種別: BRIEF PAPER
    専門分野: Electronic Circuits
    2011 年 E94.C 巻 11 号 p. 1802-1806
    発行日: 2011/11/01
    公開日: 2011/11/01
    ジャーナル 認証あり
    In this letter, an improved triple-tunable frequency synthesizer structure to achieve both high frequency resolution and fast switching speed without degradation of spurious signals (spurs) level performance is proposed. According to this structure, a high performance millimeter-wave frequency synthesizer with low spurious, low phase noise, and fast switching speed, is developed. This synthesizer driven by the direct digital synthesizer (DDS) AD9956 can adjust the output of a DDS and frequency division ratios of two variable frequency dividers (VFDs) to move the spurious components outside the loop bandwidth of the phase-locked loop (PLL). Moreover, the ADF4252 based microwave PLL can further suppress the phase noise. Experimental results from the implemented synthesizer show that remarkable performance improvements have been achieved.
  • Jhin-Fang HUANG, Huey-Ru CHUANG, Wen-Cheng LAI
    原稿種別: BRIEF PAPER
    専門分野: Electronic Circuits
    2011 年 E94.C 巻 11 号 p. 1807-1810
    発行日: 2011/11/01
    公開日: 2011/11/01
    ジャーナル 認証あり
    A 6-10-GHz broadband low noise amplifier (LNA) and transmitting amplifier (TA) for direct sequence ultra-wideband (DS-UWB) are presented. The LNA and TA are fabricated with the 0.18-µm 1P6M standard CMOS process. The CMOS LNA and TA are checked by on-wafer measurement with the DC supply voltage of 1.5V. From 6-10GHz, the broadband LNA exhibits a noise figure of 5.3-6.2dB, a gain of 11-13.8dB, a P1dB of -15.7--10.8dBm, a IIP3 of -5.5--1dBm, a DC power consumption of 12mW, and an input/output return loss higher than 11/12dB, respectively. From 6-10GHz, the broadband TA exhibits a gain of 7.6-10.5dB, a OP1dB of 2.8-6.1dBm, a OIP3 of 12.3-15.1dBm, and a PAE of 8.8-17.6% @ OP1dB, and a η of 9.7-21.1% @ OP1dB, and an input/output return loss higher than 6.8/3.2dB, respectively.
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