This paper reviews and discusses a brief history of Nyquist ADCs. Bipolar flash ADCs for early development stage of HDTV and digital oscilloscopes, a Bi-CMOS two-step flash ADC using resistive interpolation for home HDTV receivers, a CMOS two-step flash ADC using capacitive interpolation for handy camcorders, pipelined ADCs using CMOS operational amplifiers, CMOS flash ADCs using dynamic comparator and digital offset compensation, SAR ADCs using low noise dynamic comparators and MOM capacitors, and hybrid ADCs are reviewed.

Electrophysiology, which is the study of the electrical properties of biological tissues and cells, has become indispensable in modern clinical research, diagnostics, disease monitoring and therapeutics. In this paper we present a brief history of this discipline and how integrated circuit design shaped electrophysiology in the last few decades. We will discuss how biopotential amplifier design has evolved from the classical three-opamp architecture to more advanced high-performance circuits enabling long-term wearable monitoring of the autonomous and central nervous system. We will also discuss how these integrated circuits evolved to measure in-vivo neural circuits. This paper targets readers who are new to the domain of biopotential recording and want to get a brief historical overview and get up to speed on the main circuit design concepts for both wearable and in-vivo biopotential recording.

Recent years have seen a decline in the art of analog IC design even though analog interface and analog signal processing remain just as essential as ever. While there are many contributing factors, four specific pressures which contribute the most to the loss of creativity and innovation within analog practice are examined: process evolution, risk aversion, digitally assisted analog, and corporate culture. Despite the potency of these forces, none are found to be insurmountable obstacles to reinvigorating the industry. A more creative future is within our reach.

In this paper, we propose a hybrid crystal oscillator which achieves both quick startup and low steady-state power consumption. At startup, a large negative resistance is realized by configuring a Pierce oscillating circuit with a multi-stage inverter amplifier, resulting in high-speed startup. During steady-state oscillation, the oscillator is reconfigured as a class-C complementary Colpitts circuit for low power consumption and low phase noise. Prototype chips were fabricated in 65nm CMOS process technology. With Pierce-type configuration, the measured startup time and startup energy of the oscillator are reduced to 1/11 and 1/5, respectively, compared with the one without Pierce-type configuration. The power consumption during steady oscillation is 30 µW.

This paper presents a divide-by-9 injection-locked frequency divider (ILFD). It can lock onto about 6-GHz input with a locking range of 3.23GHz (58%). The basic concept of the ILFD is based on employing self-gated multiple inputs into the multiple-stage ring oscillator. A wide lock range is also realized by adapting harmonic-control circuits, which can boost specific harmonics generated by mixing. The ILFD was fabricated using a 55-nm deeply depleted channel (DDC) CMOS process. It occupies an area of 0.0210mm², and consumes a power of 14.4mW.

A power-scalable sub-sampling phase-locked loop (SSPLL) is proposed for realizing dual-mode operation; high-performance mode with good phase noise and power-saving mode with moderate phase noise. It is the most efficient way to reduce power consumption by lowering the supply voltage. However, there are several issues with the low-supply millimeter-wave (mmW) SSPLL. This work discusses some techniques, such as a back-gate forward body bias (FBB) technique, in addition to employing a CMOS deeply depleted channel process (DDC).

This paper presents a high-NIR sensitivity SOI-gate lock-in pixel with improved modulation contrast. The proposed pixel has a shallow buried channel and intermediate gates to create both a high lateral electric field and a potential barrier to parasitic light sensitivity. Device simulation results showed that parasitic light sensitivity reduced from 13.7% to 0.13% compared to the previous structure.

Energy harvesting has been widely investigated as a potential solution to supply power for Internet of Things (IoT) devices. Computing devices must operate intermittently rather than continuously, because harvested energy is unstable and some of IoT applications can be periodic. Therefore, processors for IoT devices with intermittent operation must feature a hibernation mode with zero-standby-power in addition to energy-efficient normal mode. In this paper, we describe the layout design and measurement results of a nonvolatile standard cell memory (NV-SCM) and nonvolatile flip-flops (NV-FF) with a nonvolatile memory using Fishbone-in-Cage Capacitor (FiCC) suitable for IoT processors with intermittent operations. They can be fabricated in any conventional CMOS process without any additional mask. NV-SCM and NV-FF are fabricated in a 180nm CMOS process technology. The area overhead by nonvolatility of a bit cell are 74% in NV-SCM and 29% in NV-FF, respectively. We confirmed full functionality of the NV-SCM and NV-FF. The nonvolatile system using proposed NV-SCM and NV-FF can reduce the energy consumption by 24.3% compared to the volatile system when hibernation/normal operation time ratio is 500 as shown in the simulation.

This paper presents on-chip characterization of electrostatic discharge (ESD) impacts applied on the Si-substrate backside of a flip-chip mounted integrated circuit (FC-IC) chip. An FC-IC chip has an open backside and there is a threat of reliability problems and malfunctions caused by the backside ESD. We prepared a test FC-IC chip and measured Si-substrate voltage fluctuations on its frontside by an on-chip monitor (OCM) circuit. The voltage surges as large as 200mV were observed on the frontside when a 200-V ESD gun was irradiated through a 5kΩ contact resistor on the backside of a 350μm thick Si substrate. The distribution of voltage heights was experimentally measured at 20 on-chip locations among thinned Si substrates up to 40μm, and also explained in full-system level simulation of backside ESD impacts with the equivalent models of ESD-gun operation and FC-IC chip assembly.

This brief presents a side-channel attack (SCA) technique on a high-speed asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed dual neural network based on multiple noise waveforms separately discloses sign and absolute value information of input signals which are hidden by the differential structure and high-speed asynchronous operation. The target SAR ADC and on-chip noise monitors are designed on a single prototype chip for SCA demonstration. Fabricated in 40 nm, the experimental results show the proposed attack on the asynchronous SAR ADC successfully restores the input data with a competitive accuracy within 300 mV rms error.

The complexity and scale of Networks-on-Chip (NoCs) are growing as more processing elements and memory devices are implemented on chips. However, under strict power budgets, it is also critical to lower the power consumption of NoCs for the sake of energy efficiency. In this paper, we therefore present three novel input unit designs for on-chip routers attempting to shrink their power consumption while still conserving the network performance. The key idea behind our designs is to organize buffers in the input units with characteristics of the network traffic in mind; as in our observations, only a small portion of the network traffic are long packets (composed of multiple flits), which means, it is fair to implement hybrid, asymmetric and reconfigurable buffers so that they are mainly targeting at short packets (only having a single flit), hence the smaller power consumption and area overhead. Evaluations show that our hybrid, asymmetric and reconfigurable input unit designs can achieve an average reduction of energy consumption per flit by 45%, 52.3% and 56.2% under 93.6% (for hybrid designs) and 66.3% (for asymmetric and reconfigurable designs) of the original router area, respectively. Meanwhile, we only observe minor degradation in network latency (ranging from 18.4% to 1.5%, on average) with our proposals.

In this research, we investigated the threshold voltage (V_TH) control by partial polarization of metal-ferroelectric-semiconductor field-effect transistors (MFSFETs) with 5 nm-thick nondoped HfO₂ gate insulator utilizing Kr-plasma sputtering for Pt gate electrode deposition. The remnant polarization (2P_r) of 7.2 μC/cm² was realized by Kr-plasma sputtering for Pt gate electrode deposition. The memory window (MW) of 0.58 V was realized by the pulse amplitude and width of -5/5 V, 100 ms. Furthermore, the V_TH of MFSFET was controllable by program/erase (P/E) input pulse even with the pulse width below 100 ns which may be caused by the reduction of leakage current with decreasing plasma damage.

Reducing on-chip microwave crosstalk is crucial for semiconductor spin qubit integration. Toward crosstalk reduction and qubit integration, we investigate on-chip microwave crosstalk for gate electrode pad designs with (i) etched trenches between contact pads or (ii) contact pads with reduced sizes. We conclude that the design with feature (ii) is advantageous for high-density integration of semiconductor qubits with small crosstalk (below -25 dB at 6 GHz), favoring the introduction of flip-chip bonding.

We have proposed and demonstrated a device fabrication process of physically defined quantum dots utilizing electron beam lithography employing a negative-tone resist toward high-density integration of silicon quantum bits (qubits). The electrical characterization at 3.8K exhibited so-called Coulomb diamonds, which indicates successful device operation as single-electron transistors. The proposed device fabrication process will be useful due to its high compatibility with the large-scale integration process.

The transfer distance of the wireless power transfer (WPT) system with relay coil is longer, so this technology have a better practical perspective. But the location of the relay coil has a great impact on the transmission efficiency of the WPT system, and it is not easy to analyze. In order to research the influence law of the relay coil location on the transmission efficiency and obtain the optimal location, the paper firstly proposes the concept of relay coil location factor. And based on the location factor, a novel method for studying the influence of the relay coil location on the transmission efficiency is proposed. First, the mathematical model between the transmission efficiency and the location factor is built. Next, considering the transfer distance, coil radius, coil turns and load resistance, a lot of simulations are carried out to analyze the influence of the location factor on the transmission efficiency, respectively. The influence law and the optimal location factor were obtained with different parameters. Finally, a WPT system with relay coil was built for experiments. And the experiment results verify that the theoretical analysis is correct and the proposed method can simplify the analysis progress of the influence of relay coil location on the transmission efficiency. Moreover, the proposed method and the research conclusions can provide guidance for designing the multiple coils structure WPT system.

A high-efficiency uniform/selective heating microwave oven was developed. Because the power amplifier requires high-efficiency characteristics to function as a microwave source, a free-standing Gallium Nitride (GaN) substrate was applied in this study. By applying a harmonic tuning circuit, an output power of 71 W and PAE of 73% were achieved in pulsed operation, and an output power of 63 W and PAE of 69% were achieved in CW operation. Moreover, we fabricated a prototype PA module that consists of an oscillator, a driver amplifier, PA, and other RF circuits. The output power was controlled by pulse width modulation to maintain high efficiency regardless of output power. We evaluated the arrangement of antenna polarizations to isolate each antenna. By suppressing the interference of output from adjacent antennas, it is possible to irradiate the object on the top surface of the antenna, thereby demonstrating heating characteristics with small temperature unevenness. The prototype microwave oven successfully demonstrated uniform/selective heating.

This paper provides a new method to implement substrate integrated defected ground structure (SIDGS)-based bandpass filter (BPF) with adjustable frequency and controllable bandwidth. Compared with previous literature, this method implements a new SIDGS-like resonator capable of tunable frequency in the same plane as the slotted line using a varactor diode, increasing the design flexibility. In addition, the method solves the problem that the tunable BPF constituted by the SIDGS resonator cannot control the bandwidth by introducing a T-shaped non-resonant unit. The theoretical design method and the structural design are shown. Moreover, the configured structure is fabricated and measured to show the validity of the design method in this paper.