IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
E101.C 巻, 11 号
選択された号の論文の15件中1~15を表示しています
Special Section on Electronic Displays
Regular Section
  • Sirous TALEBI, Ehsan ADIB, Majid DELSHAD
    原稿種別: PAPER
    専門分野: Electronic Circuits
    2018 年E101.C 巻11 号 p. 906-915
    発行日: 2018/11/01
    公開日: 2018/11/01
    ジャーナル 認証あり

    This paper presents a high step-up DC-DC converter for low voltage sources such as solar cells, fuel cells and battery banks. A novel non isolated Zero-Voltage Switching (ZVS) interleaved DC-DC boost converter condition is introduced. In this converter, by using coupled inductor and active clamp circuit, the stored energy in leakage inductor is recycled. Furthermore, ZVS turn on condition for both main and clamp switches are provided. The active clamp circuit suppresses voltage spikes across the main switch and the voltage of clamp capacitor leads to higher voltage gain. In the proposed converter, by applying interleaved technique, input current ripple and also conduction losses are decreased. Also, with simple and effective method without applying any additional element, the input ripple due to couple inductors and active clamp circuit is cancelled to achieve a smooth low ripple input current. In addition, the applied technique in this paper leads to increasing the life cycle of circuit components which makes the proposed converter suitable for high power applications. Finally an experimental prototype of the presented converter with 40 V input voltage, 400 V output voltage and 200 W output power is implemented which verifies the theoretical analysis.

  • Takayuki MORI, Jiro IDA
    原稿種別: PAPER
    専門分野: Semiconductor Materials and Devices
    2018 年E101.C 巻11 号 p. 916-922
    発行日: 2018/11/01
    公開日: 2018/11/01
    ジャーナル 認証あり

    In this paper, we review a super-steep subthreshold slope (SS) (<1 mV/dec) body-tied (BT) silicon on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) fabricated with 0.15 µm SOI technology and discuss the possibility of its use in ultralow voltage applications. The mechanism of the super-steep SS in the BT SOI MOSFET was investigated with technology computer-aided design simulation. The gate length/width and Si thickness optimizations promise further reductions in operation voltage, as well as improvement of the ION/IOFF ratio. In addition, we demonstrated control of the threshold voltage and hysteresis characteristics using the substrate and body bias in the BT SOI MOSFET.

feedback
Top