Maximum radiation efficiency has been derived for homogeneous electrically small antennas. The spherical wave expansion is utilized to express the radiated field and the current distribution on an antenna, and the radiation efficiency is represented by the current, which is expressed in the spherical wave expansion coefficients and the nonradiating current. By using a concept of the nonradiating current, it is shown that the maximum radiation efficiency is achieved if the antenna shape is spherical. The radiation efficiency of a spherical antenna is maximized by varying the expansion coefficients. This radiation efficiency is compared with that of the antenna which achieves the maximum gain and those of linear antennas. The comparison indicates the validity of our proposed upper limit of the radiation efficiency.

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We propose a novel phased array-fed dual-reflector antenna that reduces performance degradation caused by multiple reflection. The marked feature of the proposed configuration is that different reflector profiles are employed for the two orthogonal directions. The reflector profile in the beam-scanning section (vertical section) is set to an imaging reflector configuration, while the profile in the orthogonal non-beam-scanning section (horizontal section) is set to a ring-focus Cassegrain antenna configuration. In order to compare the proposed antenna with the conventional antenna in which multiple reflection was problematic, we designed a prototype antenna of the same size, and verified the validity of the proposed antenna. The results of the verification were that the gain in the designed central frequency increased by 0.4 dB, and the ripple of the gain frequency properties that was produced by multiple reflection was decreased by 1.1 dB. These results demonstrated the validity of the proposed antenna.

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A monolithic frequency synthesizer with wide tuning range, low phase noise and spurs was realized in 0.13 μm CMOS technology. It consists of an analog PLL, a harmonic-rejection mixer and injection-locked frequency doublers to cover the whole 6–18 GHz frequency range. To achieve a low phase noise performance, a sub-sampling PLL with non-dividers was employed. The synthesizer can achieve phase noise -113.7 dBc/Hz@100 kHz in the best case and the reference spur is below -60 dBc. The core of the synthesizer consumes about 110 mA*1.2 V.

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An artificial transmission line with variable capacitors as its shunt elements, also known as a nonlinear transmission line, can be used to generate pulsed waveforms with short durations. In this work, the variable capacitors are implemented using ferroelectric materials. Analysis and experimental results of such a ferroelectric-based artificial transmission line are presented. The differential equation that describes the nonlinear transmission line is derived and solved. The analytical expression for the solitary waves propagating along the line is found. An artificial transmission line is fabricated using thin-film barium--strontium--titanate capacitors and commercially available chip inductors. The fabrication process of the ferroelectric-based artificial transmission line is described. On-wafer characterization of the line is performed. Measurement results show that, with proper dc bias and substantial input power, a sinusoidal input waveform turns into a bell-shaped pulse train at the output, demonstrating the pulse-shaping capability of the ferroelectric-based artificial transmission line.

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A multi-port device is characterized using measurement results of a two-port Vector Network Analyzer (VNA) with four different structures. The loads used as terminations are open-, or short-circuited transmission lines (TLs), which are characterized along with Ground-Signal-Ground pads based on L-2L de-embedding method. A new characterization method for a four-port device is introduced along with its theory. The method is validated using simulation and measurement results. The characterized four-port device is a Crossing Transmission Line (CTL), mainly used for over-pass or under-pass of RF signals. Four measurement results are used to characterize the CTL. The S-parameter response of the CTL is found. To compare the results, reconstructed responses compared with the measurements. Results show good agreement between the measured and modeled results from 1 GHz to 110 GHz.

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A 10-gigabit Ethernet passive optical network (10G-EPON) is promising for the next generation of access networks. A protocol processor for 10G-EPON needs to not only achieve 10-Gbps throughput but also to have protocol extendibility for various potential services. However, the conventional protocol processor does not have the ability to install additional protocols after chip fabrication, due to its hardware-based architecture. This paper presents a software-hardware cooperative protocol processor for 10G-EPON that provides the protocol extendibility. To achieve the software-hardware cooperation, the protocol processor newly employs a software-hardware partitioning technique driven by the timing requirements of 10G-EPON and a software-hardware interface circuit with event FIFO to absorb performance difference between software and hardware. The fabricated chip with this protocol processor properly works cooperatively and is able to accept newly standardized protocols. This protocol processor enables network operators to install additional service protocols adaptively for their own services.

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A design strategy (the required ECC strength and the judgment method of the dominant error mode) of error-prediction low-density parity-check (EP-LDPC) error-correcting code (ECC) and error-recovery schemes for scaled NAND flash memories is discussed in this paper. The reliability characteristics of NAND flash memories are investigated with 1X, 2X and 3Xnm NAND flash memories. Moreover, the system-level reliability of SSDs is analyzed from the acceptable data-retention time of the SSD. The reliability of the NAND flash memory is continuously degrading as the design rule shrinks due to various problems. As a result, future SSDs will not be able to maintain system-level reliability unless advanced ECCs with signal processing are adopted. Therefore, EP-LDPC and error-recovery (ER) schemes are previously proposed to improve the reliability. The reliability characteristics such as the bit-error rate (BER) versus the data-retention time and the effect of the cell-to-cell interference on the BER are measured. These reliability characteristics obtained in this paper are stored in an SSD as a reliability table, which plays a principal role in EP-LDPC scheme. The effectiveness of the EP-LDPC scheme with the scaling of the NAND flash memory is also discussed by analyzing the cell-to-cell interference. An interference factor α is proposed to discuss the impact of the cell-to-cell coupling. As a result, the EP-LDPC scheme is assumed to be effective down to 1Xnm NAND flash memory. On the other hand, the ER scheme applies different voltage pulses to memory cells, according to the dominant error mode: program-disturb or data-retention error dominant mode. This paper examines when the error mode changes, corresponding to which pulse should be applied. Additionally, the estimation methods of the dominant error mode by ER scheme are also discussed. Finally, as a result of the system-level reliability analysis, it is concluded that the use of the EP-LDPC scheme can maintain the reliability of the NAND flash memory in 1Xnm technology node.

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We considered the oxygen diffusivity around a conductive filament of resistive switching oxides, with the aim of designing material appropriate for highly reliable non-volatile memory. Both theoretical and experimental analyses were performed for this consideration. The theoretically obtained oxygen chemical potential difference, which works as a driving force for diffusion, significantly depends on a material. Then, we experimentally confirmed that the oxygen diffusion behaviors vary greatly depending on the chemical potential differences.

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