We have succeeded in highly selective growth and positioning of Si- and SiGe-quantum-dots (QDs) on SiO₂ patterns by controlling the reactive area, whose surface is terminated with OH bonds for Si nucleation in low-pressure chemical vapor deposition (LPCVD). The selective growth of QDs on thermally grown SiO₂ line-patterns was demonstrated in LPCVD of SiH₄ and GeH₄ just after Si nucleation by controlling the early stages of Si₂H₆-LPCVD, which indicates effectively enhanced initial nucleation on OH-terminated SiO₂ surface and suppression of the nucleation and growth of dots on as-grown SiO₂ surface during Si₂H₆-LPCVD prior to SiH₄-LPCVD.

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We fabricated highly dense Si nano-columnar structures accompanied with Si nanocrystals on W-coated quartz and characterized their local electrical transport in the thickness direction in a non-contact mode by using a Rh-coated Si cantilever with pulse bias application, in which V_max, V_min, and the duty ratio were set at +3.0V, -14V, and 50%, respectively. By applying a pulse bias to the bottom W electrode with respect to a grounded top electrode made of ∼10-nm-thick Au on a sample surface, non-uniform current images in correlation with surface morphologies reflecting electron emission were obtained. The change in the surface potential of the highly dense Si nano-columnar structures accompanied with Si nanocrystals, which were measured at room temperature by using an AFM/Kelvin probe technique, indicated electron injection into and extraction from Si nanocrystals, depending on the tip bias polarity. This result is attributable to efficient electron emission under pulsed bias application due to electron charging from the top electrode to the Si nanocrystals in a positively biased duration at the bottom electrode and subsequent quasi-ballistic transport through Si nanocrystals in a negatively biased duration.

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Excimer laser annealing at 308nm in UV and semiconductor blue laser-diode annealing at 445nm were performed and compared in term of the crystallization depending on electrical properties of Si films. As a result for the thin Si films of 50nm thickness, both lasers are very effective to enlarge the grain size and to activate electrically the dopant atoms in the CVD Si film. Smooth Si surface can be obtained using blue-laser annealing of scanned CW mode. By improving the film quality of amorphous Si deposited by sputtering for subsequent crystallization, both laser annealing techniques are effective for LTPS applications not only on conventional glass but also on flexible sheet. By conducting the latter advanced annealing technique, small grain size as well as large grains can be controlled. As blue laser is effective to crystallize even rather thicker Si films of 1µm, high performance thin-film photo-sensor or photo-voltaic applications are also expected.

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We characterized bulk-heterojunction (BHJ) solar cells using a new phenylene-thiophene oligomer, 3,7-bis[5-(4-n-hexylphenyl)-2-thienyl]dibenzothiophene-5,5-dioxide (37HPTDBTSO), and phenyl-C61-butyric-acid methyl ester (PCBM). Their photovoltaic properties including current-voltage characteristics and spectrum response were investigated. It was found that 37HPTDBTSO is appraised to be valuable electron donor. The characteristics of BHJ solar cells using mixed two donors of 37HPTDBTSO and a polymer of poly(3-hexylthiophene) (P3HT) were further investigated. OSC using the blend film of mixed donars and PCBM achieved a power conversion efficiency of 0.89%.

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380keV proton irradiation effects are investigated on p-GaN and n-GaN layers in GaN-based light emitting diode (LED) by characterizing current-voltage (I-V) characteristics of p-n junction, and two-terminal resistance of p- and n-GaN on both type of layers in LED wafer. Two-terminal resistance on n-GaN kept its initial value after the 1×10¹⁴cm^-2 fluence, and was remained the same order after the 1×10¹⁵cm^-2 fluence. On the other hand, p-GaN showed sensitive increase in two-terminal resistance after the 1×10¹⁴cm^-2, and six orders of increase after the 1×10¹⁵cm^-2 fluence. Observed sensitive increase of resistivity in p-GaN is explained as a lower initial hole density in p-GaN than the initial electron density in n-GaN layer.

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To improve metal oxide semiconductor field effect transistors (MOSFET) performance, flat interface between gate insulator and silicon (Si) should be realized. In this paper, the influence of Si surface roughness on electrical characteristics of MOSFET with hafnium oxynitride (HfON) gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering was investigated for the first time. The surface roughness of Si substrate was reduced by Ar/4.9%H₂ annealing utilizing conventional rapid thermal annealing (RTA) system. The obtained root-mean-square (RMS) roughness was 0.07nm (without annealed: 0.18nm). The HfON was formed by 2nm-thick HfN deposition followed by the Ar/O₂ plasma oxidation. The electrical properties of HfON gate insulator were improved by reducing Si surface roughness. It was found that the current drivability of fabricated nMOSFETs was remarkably increased by reducing Si surface roughness. Furthermore, the reduction of Si surface roughness also leads to decrease of the 1/f noise.

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The delay time component (τ_s) of an InGaAs MOSFET caused by dynamic source resistance is discussed. On the basis of the relationship between the current density (J) and the dynamic source resistance (r_s), the value of r_s is proportional to 1/J with some offset at low current densities, whereas the offset becomes smaller in a region of high current density. The value of τ_s depends on the current in a way similar to r_s. Because the offset in the high-current-density region is proportional to the square root of the effective mass, an InGaAs MOSFET with a small mass has a shorter r_s than a Si MOSFET.

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A low VDD current mirror with deep sub-micron vertical MOSFETs is presented. The keys are new bias circuits to reduce both the minimum VDD for the operation and the sensitivity of the output current on VDD. In the simulation, our circuits reduce the minimum VDD by about 17% and the VDD sensitivity by one order both from those of the conventional. In the simulation with 90nm φ vertical MOSFET approximate models, our circuit shows about 4MΩ output resistance at 1.2-V VDD with the small temperature dependence, which is about six times as large as that with planar MOSFETs.

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Voltage Regulator Module, called VRM is a dedicated module for supplying power to microprocessor units. Recently, significant improvement of microprocessor units arises new challenges for supplying stable power. For stable and efficient control, multiphase interleaved topology is often used in today's VRM. To achieve high performance VRM, a current sensing circuit with both high efficiency and high accuracy is demanded. To achieve high accuracy, thermal dependency is a problem to be solved. In this paper, a novel alternating voltage controlled current sensing method is proposed for suppressing thermal dependency. In the proposed method, a high frequency AC voltage is superposed on the gate-ON-voltage. Then, the AC channel current is generated, and its amplitude becomes proportional to inductor current. The AC channel current is detected through a LC filter. The proposed current sensing method is very effective for realizing a current mode control DC-DC converter. In first, we simulated the relationship between our proposed current sensing method and a electrical characteristic of a power MOSFET. We used a power MOSFET device model published by a manufacture in this simulation. From the results, we find the gate parasitic capacitance of power MOSFET effects on the sensitivity of the current sensing circuit. Besides, the power dissipation in a power MOSFET increases by the frequency of applied gate ac voltage. Moreover, the proposed current sensing circuit based on the proposed method was designed and simulated the operations by Hspice. From the results, the designed current sensing circuit based on the proposed method has enough wide sensing window from 3A to 30A for VRM applications. Moreover, comparing to the conventional current sensing circuits with the MOSFET ON-resistance, the error of the proposed current sensing circuit can be decreased over 25% near 100°C.

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An energy-efficient ΔΣ modulator using a novel switched-capacitor-based integrator has been investigated. The proposed dynamic integrator uses a common-source configuration, where a MOSFET turns off after the charge redistribution is completed. Thus, only the subthreshold current flows through the integrator, resulting in high energy efficiency. A constant threshold voltage works as the virtual ground in conventional opamp-based integrators. The performance has been estimated for a 2nd-order ΔΣ modulator by transistor-level circuit simulation assuming a 0.18-µm standard CMOS technology. An FOM of 29fJ/conv-step was obtained with a peak SNDR of 82.6dB for a bandwidth and a sampling frequency of 20kHz and 5MHz, respectively.

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This paper presents a G-band triple-push voltage controlled oscillator (VCO) operating around 177GHz. The VCO, implemented in a commercial 0.13-µm RFCMOS technology, adopts a triple-push topology that is composed of 3 symmetrically coupled identical Colpitts sub-oscillators. Oscillation frequency can be tuned from 175.9GHz to 178.4GHz with varactor tuning voltage swept from 0 to 1.2V. The calibrated output power ranged from -19.7dBm to -16.6dBm depending on the oscillation frequency. The measured phase noise of the VCO is -80.2dBc/Hz at 1MHz offset. The results clearly demonstrate the possibility of applying triple-push topology for VCOs operating beyond 100GHz, enabling various high frequency applications that require tunable frequency sources.

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Optical processing of optical labels is expected for increasing processing speed in network routers. We previously proposed optical waveguide circuits for recognition of optical QAM codes by detecting a null output port. The circuits are based on a recognition circuit for QPSK codes. In the device, however, optical or electrical inverters with large dynamic range are required. In this paper, we propose optical circuits to recognize optical QAM codes by maximum output with a post-processor consisting of thresholders and logical circuits. The recognition function of the waveguide circuit is numerically proved by FD BPM.

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Many studies have reported that the single-event transient (SET) width increases with temperature. However, the mechanism for this temperature dependency is not clear, especially for an N-hit SET. In this study, TCAD simulations are carried out to study the temperature dependence of N-hit SETs in detail. Several possible factors are examined, and the results show that the temperature dependence in bulk devices is due to the decrease in the carrier mobility with temperature in both the struck NMOS and the pull-up PMOS. In contrast, the temperature dependence in SOI devices is due to the decrease in the diffusion constant and carrier lifetime with temperature, which enhances the parasitic bipolar effect.

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Two types of low-coherence millimeter-wave sources for photonic millimeter-wave ellipsometry are compared. A broadband signal (125-GHz bandwidth) or a narrowband one (0.5-GHz bandwidth) is used to measure the complex relative dielectric constants of purified water, and the narrowband signal is revealed to be suitable for accurate measurement.

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A 125MHz 64-phase delay-locked loop (DLL) is implemented for time recovery in a digital wire-line system. The architecture of the proposed DLL comprises a coarse-locking circuit added to a conventional DLL circuit, which consists of a delay line including a bias circuit, phase detector, charge pump, and loop filter. The proposed coarse-locking circuit reduces the locking time of the DLL and prevents harmonic locking, regardless of the duty cycle of the clock. In order to verify the performance of the proposed coarse-locking circuit, a 64-phase DLL with an operating frequency range of 40 to 200MHz is fabricated using a 0.18-µm 1-poly 6-metal CMOS process with a 1.8V supply. The measured rms and peak-to-peak jitter of the output clock are 3.07ps and 21.1ps, respectively. The DNL and INL of the 64-phase output clock are measured to be -0.338/+0.164 LSB and -0.464/+0.171 LSB, respectively, at an operating frequency of 125MHz. The area and power consumption of the implemented DLL are 0.3mm² and 12.7mW, respectively.

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