The individual steps of UV imprint lithography have been explained in detail from the points of manufacturing nano-structures. The applications to photonic devices have been also introduced.

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Low-temperature bonding methods of optoelectronic chips, such as laser diodes (LD) and photodiode (PD) chips, have been the focus of much interest to develop highly functional and compact optoelectronic devices, such as microsensors and communication modules. In this paper, room-temperature bonding of the optoelectronic chips with Au thin film to coined Au stud bumps with smooth surfaces (R_a: 1.3nm) using argon and hydrogen gas mixture atmospheric-pressure plasma was demonstrated in ambient air. The die-shear strength was high enough to exceed the strength requirement of MIL-STD-883F, method 2019 (×2). The measured results of the light-current-voltage characteristics of the LD chips and the dark current-voltage characteristics of the PD chips indicated no degradation after bonding.

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In this study, our recent research activities on nanophotonic devices with semiconductor quantum nanostructures are reviewed. We have developed a technique for nanofabricating of high-quality and high-density semiconductor quantum dots (QDs). On the basis of this core technology, we have studied next-generation nanophotonic devices fabricated using high-quality QDs, including (1) a high-performance QD laser for long-wavelength optical communications, (2) high-efficiency compound-type solar cell structures, and (3) single-QD devices for future applications related to quantum information. These devices are expected to be used in high-speed optical communication systems, high-performance renewable energy systems, and future high-security quantum computation and communication systems.

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The optical properties of arrays of nanoholes and nanoslits in Al films were investigated both numerically and experimentally. The choice of Al was based on its low cost and ease of processing, in addition to the fact that it has a higher plasma frequency than gold or silver, leading to lower optical losses at wavelengths of 400 to 500nm.

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We observed Ga focused-ion-beam (FIB) irradiation effect onto diamond-like carbon (DLC) free-space nanowiring (FSW) fabricated by focused-ion-beam chemical vapor deposition (FIB-CVD). A bended FIB-CVD FSW completely strained after Ga-FIB irradiation with raster scanning. This is probably caused by generation of compression stresses onto the surface of FSW, because the surface state of the nanowire changed with Ga-FIB irradiation. Transmission electron microscope (TEM) study indicates that Ga of FSW core part disappeared after Ga-FIB irradiation and a near-edge X-ray absorption fine structure (NEXAFS) analysis revealed C-Ga bond formation onto the surface. This is attributed to a movement of Ga from the core region to the surface, and/or an adsorption of Ga onto the surface by Ga-FIB scanned irradiation. The transformation of FSW is not only fascinating as physical phenomenon, but also effective for fabricating various 3-dimensional nanodevices equipped with nanowires utilized as electric wiring.

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Quantum efficiency (QE) evolution by several negative electron affinity (NEA) activation process for p-doped GaAs(100) specimen has been studied. We have carried out the surface pretreatment at 580°C or 480°C and the successive NEA activation process at room temperature (R.T.). When the NEA surface was degraded, the surface was refreshed by above pretreatment and activation process, and approximately 0.10 of QE was repeatedly obtained. It was found that the higher QE of 0.13 was achieved with the reduced pretreatment temperature at 480°C with the specific experimental conditions. This is probably caused by the residual Cs-related compounds playing an important role of the electron emission. In addition, after the multiple pretreatment and activation sequence, surface morphology of GaAs remarkably changed.

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Negative electron affinity (NEA) surfaces can be formed by alternating supply of alkali metals (e.g. Cs, Rb, K) and oxygen on semiconductor surfaces. We have studied adsorption structures of Cs on an As-terminated (2×4) (001) GaAs surface using scanning tunneling microscopy (STM). We found that the initial adsorption of Cs atoms occurs around the step sites in the form of Cs clusters and that the size of clusters is reduced by successive exposure to O₂, indicating that As-terminated (2×4) surfaces are relatively stable compared to Ga-terminated surfaces and are not broken by the Cs clusters adsorption.

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We developed an electrically driven near-infrared broadband light source based on self-assembled InAs quantum dots (QDs). By combining emissions from four InAs QD ensembles with controlled emission center wavelengths, electro-luminescence (EL) with a Gaussian-like spectral shape and approximately 85-nm bandwidth was obtained. The peak wavelength of the EL was blue-shifted from approximately 1230 to 1200 nm with increased injection current density (J). This was due to the state-filling effect: sequential filling of the discrete QD electron/hole states by supplied carriers from lower (ground state; GS) to higher (excited state; ES) energy states. The EL intensities of the ES and GS emissions exhibited different J dependence, also because of the state-filling effect. The point-spread function (PSF) deduced from the Fourier-transformed EL spectrum exhibited a peak without apparent side lobes. The half width at half maximum of the PSF was 6.5 µm, which corresponds to the estimated axial resolution of the optical coherence tomography (OCT) image obtained with this light source. These results demonstrate the effectiveness of the QD-based device for realizing noise-reduced high-resolution OCT.

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A design scheme for a high-speed differential-input limiting transimpedance amplifier (TIA) was developed. The output-stage amplifier of the TIA is investigated in detail in order to suppress undershoot and ringing in the output waveform. The amplifier also includes a peak detector for the received signal strength indicator (RSSI) output, which is used to control the optical demodulator for differential-phase-shift-keying or differential-quadrature-phase-shift-keying formats. The limiting TIA was fabricated on the basis of 1-µm emitter-width InP-based heterojunction-bipolar-transistor (HBT) IC technology. Its differential gain is 39 dB, its 3-dB bandwidth is 27 GHz, and its estimated differential transimpedance gain is 73 dBΩ. The obtained output waveform shows that the developed design scheme is effective for suppressing undershoot and ringing.

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Nearest-neighbor-search classifiers are attractive but they have high intrinsic computational demands which limit their practical application. In this paper, we propose a coprocessor for k (k with k≥1) nearest neighbor (kNN) classification in which squared Euclidean distances (SEDs) are mapped into the clock domain for realizing high search speed and energy efficiency. The minimal SED searching is carried out by weighted frequency dividers that drastically reduce the normally exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear increase. This also results in low power dissipation and high area-efficiency in comparison to the traditional method using large numbers of adders and comparators. The kNN classifier determines the class of an unknown input sample with a majority decision among the k nearest reference samples. The required majority-decision circuit is integrated with the clock-mapping-based minimal-SED searching architecture and proceeds with the classification immediately after identification of each of the k nearest references. A test chip in 180 nm CMOS technology, which can process 8 dimensions of 32 reference vectors in parallel, achieves low power dissipation of 40.32 mW (at 51.21 MHz clock frequency and 1.8 V supply voltage). Significantly, the distance search circuit consumes only 5.99 mW. Feature vectors with different dimensionality up to 2048 dimensions can be handled by the designed coprocessor due to a dimension extension circuit, enabling large flexibility for usage in different application.

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Low pin-count testing is an effective method to reduce test cost. Based on this method multi-site testing, i.e., where multiple devices are tested concurrently, can be supported under the limitation on the number of channels provided by ATE. In this work we propose a scalable test module (called STM) design that can support multi-site testing more efficiently when compared with previous work. In the previous work, the total number of devices that can be tested concurrently is usually fixed when the design for testability hardware is designed. For our STM, each STM can deal with a number of circuits to be tested at the same time. Moreover, STM is scalable, i.e., multiple STMs can work collaboratively while the ATE bandwidth still remains the same to further increase the degree of test parallelism. Our STM will be integrated with ATE and serve as an interface between ATE and circuits under test (CUT). Only four pins are required by STM to communicate with ATE, and IEEE 1149.1 Std. ports are employed to transfer test data to/from CUTs. STM has been verified via silicon proof, which contains only about 2,768 logic gates. Experiments results for a number of ISCAS and IWLS'05 benchmark circuits also demonstrate that by making good use of the scalable feature of STM, test efficiency can be enhanced significantly.

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The memory issue plays a very important role for the performance evaluation of a design of 2-Dimensional Discrete Wavelet Transform (2DDWT). A traditional 2DDWT architecture generally needs DRAM to store the input pixel and memory to store temporary results between the row and column processors. In this article, we present a system on a chip (SoC) for video/image processing. The chip integrates an analog-to-digital converter (ADC) with a highly efficient-memory 2DDWT. The latter one contains two main components only: a row processor and a column processor. With this integrated chip plus the use of feedback shift registers (FSR) in the column processor, the architecture we propose can disuse the DRAM and reduce the memory. The pipelined technique is also utilized in the proposed 2DDWT to shorten the critical path to an adder delay. Our architecture outperforms the existing architectures in that it uses less memory size and has low control complexity. It needs only a 2N register instead of a 3.5N register of traditional architectures for a one-level 2DDWT of the 5/3 Lifting-based Discrete Wavelet Transform (LDWT) in an N x N image. Our 2DDWT architecture is coded in VerilogHDL and the Synopsys Design Compiler is employed to synthesize the design with the standard-cell from TSMC 0.18 µm cell library for verification. The ADC is designed by a full-custom methodology, plays as an IP of the SoC. With the integrated SoC, based on the mix-mode design flow, the proposed work requires no external memory, which accordingly reduces the power consumption by memory access and 20 I/O PADs, it also reduces the printed circuit board (PCB) size. Moreover, the proposed SoC supports the resolution of 10 bits and can easily integrate further with the CMOS image sensor (CIS) or other IPs. This, then, completes a single chip and which is ready for a real-time wavelet-based video coding.

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I report modulation format conversion technology that maps on-off keying to 4-level pulse amplitude modulation signals. The conversion technology is based on balanced detection and intensity modulation. Two input optical on-off keying signals into a balanced photo detector produce an electrical signal that drives an intensity modulator to generate an optical pulse amplitude modulation signal. Two 20Gbit/s on-off keying signals were successfully converted into a 40Gbit/s pulse amplitude modulation signal.

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