IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
E96.C 巻, 9 号
選択された号の論文の20件中1~20を表示しています
Special Section on Recent Development of Electro-Mechanical Devices
—Papers selected from International Session on Electro-Mechanical Devices 2012 (IS-EMD2012) and other recent research results—
Regular Section
  • Kazuyuki SAITO, Masaharu TAKAHASHI, Koichi ITO
    原稿種別: PAPER
    専門分野: Electromagnetic Theory
    2013 年 E96.C 巻 9 号 p. 1178-1183
    発行日: 2013/09/01
    公開日: 2013/09/01
    ジャーナル 認証あり
    Hyperthermia is one of the modalities for cancer treatment, utilizing the difference of thermal sensitivity between tumor and normal tissue. Interstitial microwave hyperthermia is one of the heating schemes and it is applied to a localized tumor. In the treatments, heating pattern control around antennas are important, especially for the treatment in and around critical organs. This paper introduces a coaxial-dipole antenna, which is one of the thin microwave antennas and can generate a controllable heating pattern. Moreover, generations of an arbitrary shape heating patterns by an array applicator composed of four coaxial-dipole antennas are described.
  • Xin-Gang WANG, Fei WANG, Rui JIA, Rui CHEN, Tian ZHI, Hai-Gang YANG
    原稿種別: PAPER
    専門分野: Electronic Circuits
    2013 年 E96.C 巻 9 号 p. 1184-1194
    発行日: 2013/09/01
    公開日: 2013/09/01
    ジャーナル 認証あり
    This paper proposes a coarse-fine Time-to-Digital Converter (TDC), based on a Ring-Tapped Delay Line (RTDL). The TDC achieves the picosecond's level timing resolution and microsecond's level dynamic range at low cost. The TDC is composed of two coarse time measurement blocks, a time residue generator, and a fine time measurement block. In the coarse blocks, RTDL is constructed by redesigning the conventional Tapped Delay Line (TDL) in a ring structure. A 12-bit counter is employed in one of the two coarse blocks to count the cycle times of the signal traveling in the RTDL. In this way, the input range is increased up to 20.3µs without use of an external reference clock. Besides, the setup time of soft-edged D-flip-flops (SDFFs) adopted in RTDL is set to zero. The adjustable time residue generator picks up the time residue of the coarse block and propagates the residue to the fine block. In the fine block, we use a Vernier Ring Oscillator (VRO) with MOS capacitors to achieve a scalable timing resolution of 11.8ps (1 LSB). Experimental results show that the measured characteristic curve has high-level linearity; the measured DNL and INL are within ± 0.6 LSB and ± 1.5 LSB, respectively. When stimulated by constant interval input, the standard deviation of the system is below 0.35 LSB. The dead time of the proposed TDC is less than 650ps. When operating at 5 MSPS at 3.3V power supply, the power consumption of the chip is 21.5mW. Owing to the use of RTDL and VRO structures, the chip core area is only 0.35mm × 0.28mm in a 0.35µm CMOS process.
  • Song JIA, Li LIU, Xiayu LI, Fengfeng WU, Yuan WANG, Ganggang ZHANG
    原稿種別: PAPER
    専門分野: Electronic Circuits
    2013 年 E96.C 巻 9 号 p. 1195-1200
    発行日: 2013/09/01
    公開日: 2013/09/01
    ジャーナル 認証あり
    Information security has been seriously threatened by the differential power analysis (DPA). Delay-based dual-rail precharge logic (DDPL) is an effective solution to resist these attacks. However, conventional DDPL convertors have some shortcomings. In this paper, we propose improved convertor pairs based on dynamic logic and a sense amplifier (SA). Compared with the reference CMOS-to-DDPL convertor, our scheme could save 69% power consumption. As to the comparison of DDPL-to-CMOS convertor, the speed and power performances could be improved by 39% and 54%, respectively.
  • Diancheng WU, Yu LIU, Hao ZHU, Donghui WANG, Chengpeng HAO
    原稿種別: BRIEF PAPER
    専門分野: Integrated Electronics
    2013 年 E96.C 巻 9 号 p. 1201-1204
    発行日: 2013/09/01
    公開日: 2013/09/01
    ジャーナル 認証あり
    This paper presents a novel data compression method for testing integrated circuits within the framework of pattern run-length coding. The test set is firstly divided into 2n-length patterns where n is a natural number. Then the compatibility of each pattern, which can be an external type, or an internal type, is analyzed. At last, the codeword of each pattern is generated according to its analysis result. Experimental results for large ISCAS89 benchmarks show that the proposed method can obtain a higher compression ratio than existing ones.
  • Song JIA, Heqing XU, Fengfeng WU, Yuan WANG
    原稿種別: BRIEF PAPER
    専門分野: Integrated Electronics
    2013 年 E96.C 巻 9 号 p. 1205-1207
    発行日: 2013/09/01
    公開日: 2013/09/01
    ジャーナル 認証あり
    We propose a current mode sense amplifier that uses a current-mirror to increase the bitline sensing current, which dominates the sensing speed. A comparison of the sensing delay shows that the proposed sense amplifier can provide about 12.6∼15.4% improvement depending on different bitline loads in sensing speed over original WTA scheme.
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