For improving the fifth-generation mobile communication system, a highly efficient power amplifier must be designed for the base station. An outphasing amplifier is expected to be a solution for achieving high efficiency. We designed a combiner, one of the key components of the outphasing amplifier, using a serial Chireix combiner and fabricated an amplifier with a GaN HEMT, achieving 70% or more high efficiency up to 9 dB back-off power in an 800 MHz band. We also fabricated a 2 GHz-band outphasing amplifier with the same design. We applied digital predistortion (DPD) to control the balance of amplifying units in this amplifier and achieved an average efficiency of 65% under a 20 MHz modulation bandwidth.

This paper presents recent progress on high frequency and wide bandwidth GaN high power amplifiers (PAs) that are usable for high-data-rate wireless communications and modern radar systems. The key devices and design techniques for PA are described in this paper. The results of the state-of-the art GaN PAs for microwave to millimeter-wave applications and design methodology for ultra-wideband GaN PAs are shown. In order to realize high output power density, InAlGaN/GaN HEMTs were employed. An output power density of 14.8 W/mm in S-band was achieved which is 1.5 times higher than that of the conventional AlGaN/GaN HEMTs. This technique was applied to the millimeter-wave GaN PAs, and a measured power density at 96 GHz was 3 W/mm. The modified Angelov model was employed for a millimeter-wave design. W-band GaN MMIC achieved the maximum P_out of 1.15 W under CW operation. The PA with Lange coupler achieved 2.6 W at 94 GHz. The authors also developed a wideband PA. A power combiner with an impedance transformation function based on the transmission line transformer (TLT) technique was adopted for the wideband PA design. The fabricated PA exhibited an average P_out of 233 W, an average PAE of 42 %, in the frequency range of 0.5 GHz to 2.1 GHz.

In this paper, the high-power high-efficiency asymmetric Doherty power amplifiers based on high-voltage GaN HEMT devices with internal input matching for base station applications are proposed and described. For a three-way 1:2 asymmetric Doherty structures, an exceptionally high output power of 1 kW with a peak efficiency of 83% and a linear flat power gain of about 15 dB was achieved in a frequency band of 2.11-2.17 GHz, whereas an output power of 59.5 dBm with a peak efficiency of 78% and linear power gain of 12 dB and an output power of 59.2 dBm with a peak efficiency of 65% and a linear power gain of 13 dB were obtained across 1.8-2.2 GHz. To provide a high-efficiency broadband operation, the concept of inverted Doherty structure is applied and described in detail. By using a high-power broadband inverted Doherty amplifier architecture with a 2×120-W GaN HEMT transistor, a saturated power of greater than 54 dBm, a linear power gain of greater than 13 dB and a drain efficiency of greater than 50% at 7-dB power backoff in a frequency bandwidth of 1.8-2.7 GHz were obtained.

A practical Doherty amplifier design method has been developed based on an asymmetric configuration scheme. By embedding a load modulation function into matching circuits of a carrier amplifier (CA) and a peaking amplifier (PA) in the Doherty amplifier, an issue of the Doherty amplifier design is boiled down to the CA and PA matching circuit design. The method can be applied to transistors with unknown parasitic elements if optimum termination impedance conditions for the transistor are obtained from a source-/load-pull technique in simulation or measurement. The design method was applied to GaN HEMT Doherty amplifier MMICs. The fabricated 4.5-GHz-band GaN HEMT Doherty amplifier MMIC exhibited a maximum drain efficiency of 66% and a maximum power-added efficiency (PAE) of 62% at 4.1GHz, with a saturation output power of 36dBm. In addition, PAE of 50% was achieved at 4.1GHz on a 7.2-dB output back-off (OBO) condition. The fabricated 8.5-GHz-band GaN HEMT Doherty amplifier MMIC exhibited a maximum drain efficiency of 53% and a maximum PAE of 44% at 8.6GHz, with a saturation output power of 36dBm. In addition, PAE of 35% was achieved at 8.6GHz on a 6.7-dB (OBO). And, the fabricated 12-GHz-band GaN HEMT Doherty amplifier MMIC exhibited a maximum drain efficiency of 57% and a maximum PAE of 52% at 12.4GHz, with a saturation output power of 34dBm. In addition, PAE of 32% was achieved at 12.4GHz on a 9.5-dB (OBO) condition.

With the advent of 5G and external pressure to reduce greenhouse gas emissions, wireless transceivers with low power consumption are strongly desired for future cellular systems. At the same time, increased modulation order due to the evolution of cellular systems will force power amplifiers to operate at much larger output power back-off to prevent EVM degradation. This paper begins with an analysis of load modulation and asymmetrical Doherty amplifiers. Measurement results will show an apparent 60% efficiency plateau for modulated signals with a large peak-to-average power ratio (PAPR). To exceed this efficiency limitation, the second part of this paper focuses on a new amplification topology based on the amalgamation between Doherty and outphasing. Measurement results of the proposed Doherty-outphasing power amplifier (DOPA) will confirm the feasibility of the approach with a modulated efficiency greater than 70% measured at 10 dB output power back-off.

The Fifth-Generation new radio (5G NR) services that started in 2020 in Japan use a higher peak-to-average power ratio (PAPR) of a modulated signal with a maximum bandwidth of up to 100MHz and support multi-input/multi-output (MIMO) systems even in mobile handsets, compared to the Third-Generation (3G) and/or Fourth-Generation (4G) handsets. The 5G NR requires wideband operation for power amplifiers (PAs) used in handsets under a high PAPR signal condition. The 5G NR also requires a number of operating bands for the handsets. These requirements often cause significand degradation of the PA efficiency, consequently. The degradation is due to wideband and/or high PAPR operation as well as additional front-end loss between a PA and an antenna. Thus, the use of an efficiency enhancement technique is indispensable to 5G NR handset PAs. An envelope tracking (ET) is one of the most effective ways to improve the PA efficiency in the handsets. This paper gives recent progress in ET power amplifiers (ETPAs) followed by a brief introduction of ET techniques. The introduction describes a basic operation for an ET modulator that is a key component in the ET techniques and then gives a description of some kinds of ET modulators. In addition, as an example of a 5G NR ETPA, the latest experimental results for a 5G ETPA prototype are demonstrated while comparing overall efficiency of the ET modulator and PA in the ET mode with that in the average power tracking (APT) mode.

High power amplifier technologies for base transceiver stations (BTSs) for the 5th generation (5G) mobile communication systems and so-called beyond 5G (B5G) systems are reviewed. For sub-6, which is categorized into frequency range 1 (FR1) in 5G, wideband Doherty amplifiers are introduced, and a multi-band load modulation amplifier, an envelope tracking amplifier, and a digital power amplifier for B5G are explained. For millimeter wave 5G, which is categorized into frequency range 2 (FR2), GaAs and GaN MMICs operating at around 28GHz are introduced. Finally, future prospect for THz GaN devices is described.

This paper presents linearization technologies for high efficiency power amplifiers of cellular base stations. These technologies are important to actualizing highly efficient power amplifiers that reduce power consumption of the base station equipment and to achieving a sufficient non-linear distortion compensation level. It is well known that it is very difficult for a power amplifier using linearization technologies to achieve simultaneously high efficiency and a sufficient non-linear distortion compensation level. This paper presents two approaches toward addressing this technical issue. The first approach is a feed-forward power amplifier using the Doherty amplifier as the main amplifier. The second approach is a digital predistortion linearizer that compensates for frequency dependent intermodulation distortion components. Experimental results validate these approaches as effective for providing power amplification for base stations.

This paper reports the evaluation and simulated results of the nonlinear characteristics of the 4.65GHz Active Antenna System (AAS) for 5G mobile communication systems. The antenna element is composed of ±45° dual polarization shared patch antenna, and is equipped with total 64 elements with horizontal 8 × vertical 4 × 2 polarization configuration. A 32-element transceiver circuit was mounted on the back side of the antenna printed circuit board. With the above circuit configuration, a full digital beamforming method has been adopted that can realize high frequency utilization efficiency by using the Sub6GHz-band massive element AAS, and excellent spatial multiplexing performance by Massive MIMO has been pursued. However, it was found that the Downlink (DL) SINR (Signal to Interference and Noise Ratio) to each terminal deteriorated because of the nonlinear distorted radiation as the transmission output power was increased in the maximum rated direction. Therefore, it has been confirmed that the spatial multiplexing performance in the high output power region is significantly improved by installing DPD. In order to clarify the affection of nonlinear distorted radiation on spatial multiplexing performance, the radiation patterns were measured using OFDM signal (subcarrier spacing 60kHz × 1500 subcarriers in 90MHz bandwidth) in an anechoic chamber. And by the simulated analysis for the affection of nonlinear distortion on null characteristic, the accuracy of nulls generated in each user terminal direction does not depend on the degree of nonlinearity, but is affected by the residual amplitude and phase variation among all transmitters and receivers after calibration (CAL). Therefore, it was clarified that the double compensation configuration of DPD and high-precision CAL is effective for achieving excellent Massive MIMO performance. This paper is based on the IEICE Japanese Transactions on Communications (Vol.J102-B, No.11, pp.816-824, Nov. 2019).

Research on wireless power transmission technology is being actively conducted, and studies on spatial transmission methods such as SSPS are currently underway for applications such as power transfer to the upper part of steel towers and power transfer to flying objects such as drones. To enable such applications, it is necessary to examine the configuration of the power-transfer and power-receiving antennas and to improve the RF-DC conversion efficiency (hereinafter referred to as conversion efficiency) of the rectifier circuit on the power-receiving antenna. To improve the conversion efficiency, various methods that utilize full-wave rectification rather than half-wave rectification have been proposed. However, these come with problems such as a complicated circuit structure, the need for additional capacitors, the selection of components at high frequencies, and a reduction in mounting yield. In this paper, we propose a method to improve the conversion efficiency by loading a high-impedance microstrip line as a feedback line in part of the rectifier circuit. We analyzed a class-F rectifier circuit using circuit analysis software and found that the conversion efficiency of the conventional configuration was 54.2%, but the proposed configuration was 69.3%. We also analyzed a measuring circuit made with a discrete configuration in the 5.8-GHz band and found that the conversion efficiency was 74.7% at 24dBm input.

This paper demonstrates that a 360° radio-frequency phase detector consisting of a combination of symmetrical mixers and 45° phase shifters with tunable devices can achieve a low phase-detection error over a wide frequency range. It is shown that the phase detection error does not depend on the voltage gain of the 45° phase shifter. This allows the usage of tunable devices as 45° phase shifters for a wide frequency range with low phase-detection errors. The fabricated phase detector having tunable low-pass filters as the tunable device demonstrates phase detection errors lower than 2.0° rms in the frequency range from 3.0 GHz to 10.5 GHz.

Realizing frequency rectangular characteristics using a planar circuit made of a normal conductor material such as a printed circuit board (PCB) is difficult. The reason is that the corners of the frequency response are rounded by the effect of the low unloaded quality factors of the resonators. Rectangular frequency characteristics are generally realized by a low-noise amplifier (LNA) with flat gain characteristics and a high-order bandpass filter (BPF) with resonators having high unloaded quality factors. Here, we use an LNA and a fourth-order flat passband BPF made of a PCB to realize the desired characteristics. We first calculate the signal and noise powers to confirm any effects from insertion loss caused by the BPF. Next, we explain the design and fabrication of an LNA, since no proper LNAs have been developed for this research. Finally, the rectangular frequency characteristics are shown by a circuit combining the fabricated LNA and the fabricated flat passband BPF. We show that rectangular frequency characteristics can be realized using a flat passband BPF technique.

This paper demonstrates 300GHz terahertz wireless communication using CMOS transmitter (TX) and receiver (RX) modules targeting sixth-generation (6G). To extend communication distance, CMOS modules with WR-3.4 waveguide interface and a high-gain antenna of 40dBi Cassegrain antenna are designed, achieving 36Gbps throughput at a 1m communication distance. Besides, in order to support orthogonal frequency-division multiplexing (OFDM), a self-heterodyne architecture is introduced, which effectively cancels the phase noise in multi-carrier modulation. As a proof-of-concept (PoC), the paper successfully demonstrates real-time video transfer at a 10m communication distance using fifth-generation (5G) based OFDM at the 300GHz frequency band.

In this paper, we present the transmission characteristics control of a 125 GHz-band split-ring resonator (SRR) bandstop filter by coupling an alignment-free lattice pattern. We demonstrate that the transmission characteristics of the SRR filter can be controlled by coupling the lattice pattern; however, the required accuracy of alignment between the SRR filter and lattice pattern was below 200 µm. Therefore, we designed an alignment-free lattice pattern whose unit cell size is different from that of the SRR unit cell. S₂₁ of the SRR bandstop filter changes from -38.7 to -4.0 dB at 125 GHz by arranging the alignment-free lattice pattern in close proximity to the SRR stopband filter without alignment. A 10 Gbit/s data transmission can be achieved over a 125 GHz-band wireless link by setting the alignment-free lattice pattern substrate just above the SRR bandstop filter.

Long-range radars (LRRs) for higher level autonomous driving (AD) will require more antennas than simple driving assistance. The point at issue here is 50-60% of the LRR module area is used for antennas. To miniaturize LRR modules, we use horn and lens antenna with highly efficient gain. In this paper, we propose two high-density implementation techniques for radio-frequency (RF) front-end using horn and lens antennas. In the first technique, the gap between antennas was eliminated by taking advantage of the high isolation performance of horn and lens antennas. In the second technique, the RF front-end including micro-strip-lines, monolithic microwave integrated circuits, and peripheral parts is placed in the valley area of each horn. We fabricated a prototype LRR operating at 77 GHz with only one printed circuit board (PCB). To detect vehicles horizontally and vertically, this LRR has a minimum antenna configuration of one Tx antenna and four Rx antennas placed in 2×2 array, and 30 mm thickness. Evaluation results revealed that vehicles could be detected up to 320 m away and that the horizontal and vertical angle error was less than +/- 0.2 degrees, which is equivalent to the vehicle width over 280 m. Thus, horn and lens antennas implemented using the proposed techniques are very suitable for higher level AD LRRs.

Applications of continuous-time (CT) comparator include relaxation oscillators, pulse width modulators, and so on. CT comparator receives a differential input and outputs a strobe ideally when the differential input crosses zero. Unlike the DT comparators with positive feedback circuit, amplifiers consuming static power must be employed in CT comparators to amplify the input signal. Therefore, minimization of comparator delay under the constraint of power consumption often becomes an issue. This paper analyzes transient behavior of a CT comparator. Using “constant delay approximation”, the comparator delay is derived as a function of input slew rate, number of stages of the preamplifier, and device parameters in each block. This paper also discusses optimum design of the CT comparator. The condition for minimum comparator delay is derived with keeping power consumption constant. The results include that the optimum DC gain of the preamplifier is e∼e³ per stage depending on the element which dominates load capacitance of the preamplifier.

A method for detecting the timing of photodiode (PD) saturation without using an in-pixel time-to-digital converter (TDC) is proposed. Detecting PD saturation time is an approach to extend the dynamic range of a CMOS image sensor (CIS) without multiple exposures. In addition to accumulated charges in a PD, PD saturation time can be used as a signal related to light intensity. However, in previously reported CISs with detecting PD saturation time, an in-pixel TDC is used to detect and store PD saturation time. That makes the resolution of a CIS lower because an in-pixel TDC requires a large area. As for the proposed pixel circuit, PD saturation time is detected and stored as a voltage in a capacitor. The voltage is read and converted to a digital code by a column ADC after an exposure. As a result, an in-pixel TDC is not required. A signal-processing and calibration method for combining two signals, which are saturation time and accumulated charges, linearly are also proposed. Circuit simulations confirmed that the proposed method extends the dynamic range by 36 dB and its total dynamic range to 95 dB. Effectiveness of the calibration was also confirmed through circuit simulations.

This paper proposes an area- and energy-efficient DLL-based body bias generator (BBG) for minimum energy operation that controls p-well and n-well bias independently. The BBG can minimize total energy consumption of target circuits under a skewed process condition between nMOSFETs and pMOSFETs. The proposed BBG is composed of digital cells compatible with cell-based design, which enables energy- and area-efficient implementation without additional supply voltages. A test circuit is implemented in a 65-nm FDSOI process. Measurement results using a 32-bit RISC processor on the same chip show that the proposed BBG can reduce energy consumption close to a minimum within a 3% energy loss. In this condition, energy and area overheads of the BBG are 0.2% and 0.12%, respectively.

In general, since the in-band noise of phase-locked loops (PLLs) is mainly caused by charge pumps (CPs), large-size transistors that occupy a large area are used to improve in-band noise of CPs. With the high demand for low phase noise in recent high-performance communication systems, the issue of the trade-off between occupied area and noise in conventional CPs has become significant. A noise-canceling CP circuit is presented in this paper to mitigate the trade-off between occupied area and noise. The proposed CP can achieve lower noise performance than conventional CPs by performing additional noise cancelation. According to the simulation results, the proposed CP can reduce the current noise to 57% with the same occupied area, or can reduce the occupied area to 22% compared with that of the conventional CPs at the same noise performance. We fabricated a prototype of the proposed CP embedded in a 28-GHz LC-PLL using a 16-nm FinFET process, and 1.2-dB improvement in single sideband integrated phase noise is achieved.