This paper surveys advances in biomedical processor SoC technology for healthcare application and reviews state-of-the-art architecture and circuits used in SoC integration. Particularly, this paper categorizes and describes techniques for improving power efficiency in communication, computation, and sensing. Additionally, it surveys accuracy enhancement techniques for bio-signal measurement and recognition. Finally, we have discussed the potential new directions for development as well as research.

Approximate computing is a promising paradigm to realize fast, small, and low power characteristics, which are essential for modern applications, such as Internet of Things (IoT) devices. This paper proposes the Carry-Predicting Adder (CPredA), an approximate adder that is scalable relative to accuracy and power consumption. The proposed CPredA improves the accuracy of a previously studied adder by performing carry prediction. Detailed simulations reveal that, compared to the existing approximate adder, accuracy is improved by approximately 50% with comparable energy efficiency. Two application-level evaluations demonstrate that the proposed approximate adder is sufficiently accurate for practical use.

This study proposes a design and calibration method for a small-footprint, low-frequency, and low-power gate leakage timer using a differential leakage technique for IoT applications. The proposed gate leakage timer is different from conventional ones because it is composed of two leakage sources and exploits differential leakage current for the charging capacitor. This solution alleviates the inherent trade-off between small-footprint and low-frequency in the conventional gate leakage timer. Furthermore, a calibration method to suppress variations of the output frequency is proposed in this paper. To verify the effectiveness of the proposed gate leakage timer, a test chip was fabricated using 55-nm-DDC-CMOS technology. The test chip successfully demonstrates the highest figure of merit (FoM) of the product of the capacitor area (0.072µm²) and output frequency (0.11Hz), which corresponds to an improvement by a factor of 2,121 compared to the conventional one. It also demonstrates the operation with 4.5pW power consumption. The total footprint can be reduced to be 28µm², which enables low-cost and low-power IoT edges. The scaling scenario shows that the proposed technique is conducive to technology scaling.

This paper presents a high power efficient pulse VCO with tail-filter for the chip-scale atomic clock (CSAC) application. The stringent power and clock stability specifications of next-generation CSAC demand a VCO with ultra-low power consumption and low phase noise. The proposed VCO architecture aims for the high power efficiency, while further reducing the phase noise using tail filtering technique. The VCO has been implemented in a standard 45nm SOI technology for validation. At an oscillation frequency of 5.0GHz, the proposed VCO achieves a phase noise of -120dBc/Hz at 1MHz offset, while consuming 1.35mW. This translates into an FoM of -191dBc/Hz.

A 1-Transistor 4-Magnetic Tunnel Junction (1T-4MTJ) memory cell has been proposed for field type of Magnetic Random Access Memory (MRAM). Proposed 1T-4MTJ memory cell array is achieved 44% higher density than that of conventional 1T-1MTJ thanks to the common access transistor structure in a 4-bit memory cell. A self-reference sensing scheme which can read out with write-back in four clock cycles has been also proposed. Furthermore, we add to estimate with considering sense amplifier variation and show 1T-4MTJ cell configuration is the best solution in IoT applications. A 1-Mbit MRAM test chip is designed and fabricated successfully using 130-nm CMOS process. By applying 1T-4MTJ high density cell and partially embedded wordline driver peripheral into the cell array, the 1-Mbit macro size is 4.04 mm2 which is 35.7% smaller than the conventional one. Measured data shows that the read access is 55 ns at 1.5 V typical supply voltage and 25C. Combining with conventional high-speed 1T-1MTJ caches and proposed high-density 1T-4MTJ user memories is an effective on-chip hierarchical non-volatile memory solution, being implemented for low-power MCUs and SoCs of IoT applications.

Soft error jeopardizes the reliability of semiconductor devices, especially those working at low voltage. In recent years, silicon-on-thin-box (SOTB), which is a FD-SOI device, is drawing attention since it is suitable for ultra-low-voltage operation. This work evaluates the contributions of SRAM, FF and combinational circuit to chip-level soft error rate (SER) based on irradiation test results. For this evaluation, this work performed neutron irradiation test for characterizing single event transient (SET) rate of SOTB and bulk circuits at 0.5 V. Using the SBU and MCU data in SRAMs from previous work, we calculated the MBU rate with/without error correcting code (ECC) and with 1/2/4-col MUX interleaving. Combining FF error rates reported in literature, we estimated chip-level SER and each contribution to chip-level SER for embedded and high-performance processors. For both the processors, without ECC, 95% errors occur at SRAM in both SOTB and bulk chips at 0.5 V and 1.0 V, and the overall chip-level SERs of the assumed SOTB chip at 0.5 V is at least 10 x lower than that of bulk chip. On the other hand, when ECC is applied to SRAM in the SOTB chip, SEUs occurring at FFs are dominant in the high-performance processor while MBUs at SRAMs are not negligible in the bulk embedded chips.

A number of all-optical signal processing schemes based on nonlinear optical effects have been proposed and demonstrated for use in future photonic networks. Since various modulation formats have been developed for optical communication systems, all-optical converters between different modulation formats will be a key technology to connect networks transparently and efficiently. This paper reviews our recent works on all-optical modulation format conversion technologies in order to highlight the fundamental principles and applications in variety of all-optical signal processing schemes.

The needs for ultra-high speed short- to medium-reach optical fiber links beyond 100-Gbit/s is becoming larger and larger especially for intra and inter-data center applications. In recent intensity-modulated/direct-detection (IM/DD) high-speed optical transceivers with the channel bit rate of 50 and/or 100 Gbit/s, multilevel pulse amplitude modulation (PAM) is finally adopted to lower the signaling speed. To further increase the transmission capacity for the next-generation optical transceivers, various signaling techniques have been studied, especially thanks to advanced digital signal processing (DSP). In this paper, we review various signaling technologies proposed so far for short-to-medium reach applications.

Ethernet has become an indispensable technology for communications, and has come into use for many applications. At the IEEE, high-speed standardization has been discussed and has seen the adoption of new technologies such as multi-level modulation formats, high baud rate modulation and dense wave length division multiplexing. The MSA transceiver form factor has also been discussed following IEEE standardization. Optical devices such as TOSA and ROSA have been required to become more compact and higher-speed, because each transceiver form factor has to be miniaturized for high-density construction. We introduce the technologies for realizing 100GbE and those applicable to 400GbE. We also discuss future packages for optical devices. There are many similarities between optical device packages and electrical device packages, and we predict that optical device packages will follow the trends seen in electrical devices. But there are also differences between optical and electrical devices. It is necessary to utilize new technology for specific optical issues to employ advanced electrical packaging and catch up the trends.

Optical I/O core based on silicon photonics technology and optical/electrical assembly was developed as a fingertip-size optical module with high bandwidth density, low power consumption, and high temperature operation. The advantages of the optical I/O core, including hybrid integration of quantum dot laser diode and optical pin, allow us to achieve 300-m transmission at 25Gbps per channel when optical I/O core is mounted around field-programmable gate array without clock data recovery.

We developed a high-frequency and integrated design based on a flip-chip interconnection technique (Hi-FIT) as a wire-free interconnection technique that provides a high modulation bandwidth. The Hi-FIT can be applied to various high-speed (>100 Gbaud) optical devices. The Hi-FIT EA-DFB laser module has a 3-dB bandwidth of 59 GHz. And with a 4-intensity-level pulse amplitude modulation (PAM) operation at 107 Gbaud, we obtained a bit-error rate (BER) of less than 3.8×10^-3, which is an error-free condition, by using a 7%-overhead (OH) hard-decision forward error correction (HD-FEC) code, even after a 10-km SMF transmission. The 3-dB bandwidth of the Hi-FIT employing an InP-MZM sub-assembly was more than 67 GHz, which was the limit of our measuring instrument. We also demonstrated a 120-Gbaud rate IQ modulation.

We present InP-based photodetectors monolithically integrated with a 90^° hybrid toward over 400Gb/s coherent transmission systems. To attain a wide 3-dB bandwidth of more than 40GHz for 400Gb/s dual-polarization (DP)-16-ary quadrature amplitude modulation (16QAM) and 600Gb/s DP-64QAM through 64GBaud operation, A p-i-n photodiode structure consisting of a GaInAs thin absorption and low doping n-typed InP buffer layers was introduced to overcome the trade-off between short carrier transit time and low parasitic capacitance. Additionally, this InP buffer layer contributes to the reduction of propagation loss in the 90^° hybrid waveguide, that is, this approach allows a high responsivity as well as wide 3-dB bandwidth operation. The coherent receiver module for the C-band (1530nm - 1570nm) operation indicated the wide 3-dB bandwidth of more than 40GHz and the high receiver responsivity of more than 0.070A/W (Chip responsivity within the C-band: 0.130A/W) thanks to photodetectors with this photodiode design. To expand the usable wavelengths in wavelength-division multiplexing toward large-capacity optical transmission, the photodetector integrated with the 90^° hybrid optimized for the L-band (1565nm - 1612nm) operation was also fabricated, and exhibited the high responsivity of more than 0.120A/W over the L-band. Finally, the InP-based monolithically integrated photonic device consisting of eight-channel p-i-n photodiodes, two 90^° hybrids and a beam splitter was realized for the miniaturization of modules and afforded the reduction of the total footprint by 70% in a module compared to photodetectors with the 90^° hybrid and four-channel p-i-n photodiodes.

We report our recent progress in silicon photonics integrated device technology targeting on-chip-level large-capacity optical interconnect applications. To realize high-capacity data transmission, we successfully developed on-package-type silicon photonics integrated transceivers and demonstrated simultaneous 400 Gbps operation. 56 Gbps pulse-amplitude-modulation (PAM) 4 and wavelength-division-multiplexing technologies were also introduced to enhance the transmission capacity.

We have proposed and demonstrated a mode selective active-MMI (multimode interferometer) laser diode as a mode selective light source so far. This laser diode features; 1) lasing at a selected space mode, and 2) high modulation bandwidth. Based on these, it is expected to enable high speed interconnection into future personal and mobile devices. In this paper, we explain the mode selection, and the high speed modulation principles. Then, we present our recent results concerning high speed frequency response of the fundamental and first order space modes.

This paper presents a method combining array signal processing and adaptive noise cancellation to suppress unwanted ambient interferences in in situ measurement of radiated emissions of equipment. First, the signals received by the antenna array are processed to form a main data channel and an auxiliary data channel. The main channel contains the radiated emissions of the equipment under test and the attenuated ambient interferences. The auxiliary channel only contains the attenuated ambient interferences. Then, the adaptive noise cancellation technique is used to suppress the ambient interferences based on the correlation of the interferences in the main and auxiliary channels. The proposed method overcomes the problem that the ambient interferences in the two channels of the virtual chamber method are not correlated, and realizes the suppression of multi-source ambient noises in the use of fewer array elements. The results of simulation and experiment show that the proposed method can effectively extract radiated emissions of the equipment under test in complex electromagnetic environment. Finally, discussions on the effect of the beam width of the main channel and the generalization of the proposed method to three dimensionally distributed signals are addressed.

To address the bandwidth bottleneck that exists between LSI chips, we have proposed a novel, high-sensitivity receiver circuit for differential optical transmission on a silicon optical interposer. Both anodes and cathodes of the differential photodiodes (PDs) were designed to be connected to a transimpedance amplifier (TIA) through coupling capacitors. Reverse bias voltage was applied to each of the differential PDs through load resistance. The proposed receiver circuit achieved double the current signal amplitude of conventional differential receiver circuits. The frequency response of the receiver circuit was analyzed using its equivalent circuit, wherein the temperature dependence of the PD was implemented. The optimal load resistances of the PDs were determined to be 5kΩ by considering the tradeoff between the frequency response and bias voltage drop. A small dark current of the PD was important to reduce the voltage drop, but the bandwidth degradation was negligible if the dark current at room temperature was below 1µA. The proposed circuit achieved 3-dB bandwidths of 18.9 GHz at 25^°C and 13.7 GHz at 85^°C. Clear eye openings in the TIA output waveforms for 25-Gbps 2⁷-1 pseudorandom binary sequence signals were obtained at both temperatures.