Special Section on Fundamentals and Applications of Advanced Semiconductor Devices
-
Tanemasa ASANO
2009 年 E92.C 巻 5 号 p.
593
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
-
Tetsuo ENDOH, Yuto NORIFUSA
原稿種別: PAPER
2009 年 E92.C 巻 5 号 p.
594-597
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
In this paper, the device performances of sub-10nm Vertical MOSFETs are investigated. One of the drawbacks of conventional planar MOSFETs is that in the sub-10nm generation, its cutoff leakage current increases due to the short channel effects, but even more, its driving current decreases due to the quantum mechanical confinement effects such as the sub-band effect and the depletion of the inversion layer. It is shown for the first time that by downscaling the silicon pillar diameter from 20nm to 4nm, the Vertical MOSFET increases its driving current per footprint to about 2 times and suppresses its total cutoff leakage current per footprint to less than 1/60 at the same time. Moreover, the mechanisms of these improvements of Vertical MOSFET performances are clarified. The results of this work show that Vertical MOSFETs can overcome the drawbacks of conventional planar MOSFETs and achieve the high device performance through the sub-10nm generation.
抄録全体を表示
-
Tetsuo ENDOH, Yuto NORIFUSA
原稿種別: PAPER
2009 年 E92.C 巻 5 号 p.
598-602
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
In this study, I have numerically investigated the temperature distribution of n-type Si Nano Wire MOS Transistor induced by the self-heating effect by using a 3-D device simulator. The dependencies of temperature distribution within the Si Nano Wire MOS Transistor on both its gate length and width of the Si nano wire were analyzed. First, it is shown that the peak temperature in Si Nano Wire MOS Transistor increases by 100K with scaling the gate length from 54nm to 14nm in the case of a 50nm width Si nano wire. Next, it is found that the increase of its peak temperature due to scaling the gate length can be suppressed by scaling the size of the Si nano wire, for the first time. The peak temperature suppresses by 160K with scaling the Si nano wire width from 50nm to 10nm in the case of a gate length of 14nm. Furthermore, the heat dissipation in the gate, drain, and source direction are analyzed, and the analytical theory of the suppression of the temperature inside Si Nano Wire MOSFET is proposed. This study shows very useful results for future Si Nano Wire MOS Transistor design for suppressing the self-heating effect.
抄録全体を表示
-
Tetsuo ENDOH, Masashi KAMIYANAGI
原稿種別: PAPER
2009 年 E92.C 巻 5 号 p.
603-607
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
In this paper, we propose the novel Dynamic Feedback (DF-) MCML technique for high-speed and high-gain MCML type latch. The concept of the proposed DF-MCML technique is as follows; the output node signal is feedbacked to the input node in Sampling-Mode, and the output node is opened from the input node in Holding-Mode. It is shown by analytic theory that by this dynamic feedback sequence, both stability and sensibility of latch in Sampling-Mode is exponentially improved, and the gain of latch in Holding-Mode is drastically increased. Finally, we have numerically investigated the circuit performance of the novel DF-MCML type latch in comparison with the conventional MCML type latch by using P-Spice simulator. The maximum operation frequency of 180nm DF-MCML type latch reaches over 20GHz that is 2 times than the conventional MCML type latch. It is made clear that the proposed novel Dynamic Feedback MCML technique is suitable for over 10GHz high-speed and high-gain Si ULSIs.
抄録全体を表示
-
Masataka MIYAKE, Daisuke HORI, Norio SADACHIKA, Uwe FELDMANN, Mitiko M ...
原稿種別: PAPER
2009 年 E92.C 巻 5 号 p.
608-615
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
We analyze the carrier dynamics in MOSFETs under low-voltage operation. For this purpose the displacement (charging/discharging) current, induced during switching operations is studied experimentally and theoretically for a 90nm CMOS technology. It is found that the experimental transient characteristics can only be well reproduced in the circuit simulation of low voltage applications by considering the carrier-transit delay in the compact MOSFET model. Long carrier transit delay under the low voltage switching-on operation results in long duration of the displacement current flow. On the other hand, the switching-off characteristics are independent of the bias condition.
抄録全体を表示
-
Kazuhiro SHIMANOE, Katsunori MAKIHARA, Mitsuhisa IKEDA, Seiichi MIYAZA ...
原稿種別: PAPER
2009 年 E92.C 巻 5 号 p.
616-619
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
We have studied the formation of Pd-nanodots on SiO
2 from ultrathin Pd films being exposed to remote hydrogen plasma at room temperature, in which parameters such as the gas pressure and input power to generate H
2 plasma and the Pd film thickness were selected to get some insights into surface migration of Pd atoms induced with atomic hydrogen irradiation and resultant agglomeration with cohesive action. The areal dot density was controlled in the range from ∼3.4 to ∼ 6.5×10
11 cm
-2 while the dot size distribution was changed from ∼7 to ∼1.5 in average dot height with ∼40% variation in full-width at half maximum. We also fabricated MOS capacitors with a Pd-nanodots floating gate and confirmed the flat-band voltage shift in capacitance-voltage characteristic due to electron injection to and emission from the dots floating gate.
抄録全体を表示
-
Seongjae CHO, Jung Hoon LEE, Gil Sung LEE, Jong Duk LEE, Hyungcheol SH ...
原稿種別: PAPER
2009 年 E92.C 巻 5 号 p.
620-626
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
Recently, various types of 3-D nonvolatile memory (NVM) devices have been researched to improve the integration density [1]-[3]. The NVM device of pillar structure can be considered as one of the candidates [4], [5]. When this is applied to a NAND flash memory array, bottom end of the device channel is connected to the bulk silicon. In this case, the current in vertical direction varies depending on the thickness of silicon channel. When the channel is thick, the difference of saturation current levels between on/off states of individual device is more obvious. On the other hand, when the channel is thin, the on/off current increases simultaneously whereas the saturation currents do not differ very much. The reason is that the channel potential barrier seen by drain electrons is lowered by read voltage on the opposite sidewall control gate. This phenomenon that can occur in 3-D structure devices due to proximity can be called gate-induced barrier lowering (GIBL). In this work, the dependence of GIBL on silicon channel thickness is investigated, which will be the criteria in the implementation of reliable ultra-small NVM devices.
抄録全体を表示
-
Jongwook JEON, Ickhyun SONG, Jong Duk LEE, Byung-Gook PARK, Hyungcheol ...
原稿種別: PAPER
2009 年 E92.C 巻 5 号 p.
627-634
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
In this paper, a compact channel thermal noise model for short-channel MOSFETs is presented and applied to the radio frequency integrated circuit (RFIC) design. Based on the analysis of the relationship among different short-channel effects such as velocity saturation effect (VSE), channel-length modulation (CLM), and carrier heating effect (CHE), the compact model for the channel thermal noise was analytically derived as a simple form. In order to simulate MOSFET's noise characteristics in circuit simulators, an appropriate methodology is proposed. The used compact noise model is verified by comparing simulated results to the measured data at device and circuit level by using 65nm and 130nm CMOS technologies, respectively.
抄録全体を表示
-
Dong-Shong LIANG, Kwang-Jow GAN, Cheng-Chi TAI, Cher-Shiung TSAI
原稿種別: PAPER
2009 年 E92.C 巻 5 号 p.
635-638
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
The paper demonstrates a novel two-peak negative differential resistance (NDR) circuit combining Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT). Compared to the resonant-tunneling diode, MOS-HBT-NDR has two major advantages in our circuit design. One is that the fabrication of this MOS-HBT-NDR-based application can be fully implemented by the standard BiCMOS process. Another is that the peak current can be effectively adjusted by the controlled voltage. The peak-to-valley current ratio is about 4136 and 9.4 at the first and second peak respectively. It is very useful for circuit designers to consider the NDR-based applications.
抄録全体を表示
-
Wan Zuha WAN HASAN, Izhal ABD HALIN, Roslina MOHD SIDEK, Masuri OTHMAN
原稿種別: PAPER
2009 年 E92.C 巻 5 号 p.
639-646
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
Testing and diagnosis techniques play a key role in the advance of semiconductor memory technology. The challenge of failure detection has created intensive investigation on efficient testing and diagnosis algorithm for better fault coverage and diagnostic resolution. At present, March test algorithm is used to detect and diagnose all faults related to Random Access Memories. However, the test and diagnosis process are mainly done manually. Due to this, a systematic approach for developing and evaluating memory test algorithm is required. This work is focused on incorporating the March based test algorithm using a software simulator tool for implementing a fast and systematic memory testing algorithm. The simulator allows a user through a GUI to select a March based test algorithm depending on the desired fault coverage and diagnostic resolution. Experimental results show that using the simulator for testing is more efficient than that of the traditional testing algorithm. This new simulator makes it possible for a detailed list of stuck-at faults, transition faults and coupling faults covered by each algorithm and its percentage to be displayed after a set of test algorithms has been chosen. The percentage of diagnostic resolution is also displayed. This proves that the simulator reduces the trade-off between test time, fault coverage and diagnostic resolution. Moreover, the chosen algorithm can be applied to incorporate with memory built-in self-test and diagnosis, to have a better fault coverage and diagnostic resolution. Universities and industry involved in memory Built-in-Self test, Built-in-Self repair and Built-in-Self diagnose will benefit by saving a few years on researching an efficient algorithm to be implemented in their designs.
抄録全体を表示
-
Sang Hyuk PARK, Sangwoo KANG, Seongjae CHO, Dong-Seup LEE, Jung Han LE ...
原稿種別: PAPER
2009 年 E92.C 巻 5 号 p.
647-652
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
A Recessed-Channel Dual-Gate Single Electron Transistor (RCDG-SET) which has the possibility of room temperature operation is proposed. Side gates of a RCDG-SET form electrical tunneling barriers around a recessed channel, which is newly introduced. Not only gate but also a recessed channel is self aligned to source and drain. Characteristics of a RCDG-SET are compared with those of previous DG-SETs through device simulation (SILVACO). Due to a recessed channel and a self aligned structure, MOSFET current which causes low Peak-to-Valley Current Ratio (PVCR) is suppressed. This property of a RCDG-SET is expected to contribute for room temperature operation.
抄録全体を表示
-
Yoon KIM, Seongjae CHO, Gil Sung LEE, Il Han PARK, Jong Duk LEE, Hyung ...
原稿種別: PAPER
2009 年 E92.C 巻 5 号 p.
653-658
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
We propose a 3-dimensional terraced NAND flash memory. It has a vertical channel so it is possible to make a long enough channel in 1F
2 size. And it has 3-dimensional structure whose channel is connected vertically along with two stairs. So we can obtain high density as in the stacked array structure, without silicon stacking process. We can make NAND flash memory with 3F
2 cell size. Using SILVACO ATLAS simulation, we study terraced NAND flash memory characteristics such as program, erase, and read. Also, its fabrication method is proposed.
抄録全体を表示
-
Doo-Hyun KIM, Il Han PARK, Seongjae CHO, Jong Duk LEE, Hyungcheol SHIN ...
原稿種別: PAPER
2009 年 E92.C 巻 5 号 p.
659-663
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
This paper presents a detailed study of the retention characteristics in scaled multi-bit SONOS flash memories. By calculating the oxide field and tunneling currents, we evaluate the charge trapping mechanism. We calculate transient retention dynamics with the ONO fields, trapped charge, and tunneling currents. All the parameters were obtained by physics-based equations and without any fitting parameters or optimization steps. The results can be used with nanoscale nonvolatile memory. This modeling accounts for the
VT shift as a function of trapped charge density, time, silicon fin thickness and type of trapped charge, and can be used for optimizing the ONO geometry and parameters for maximum performance.
抄録全体を表示
-
Masahiro KONDA, Akinobu TERAMOTO, Tomoyuki SUWA, Rihito KURODA, Tadahi ...
原稿種別: PAPER
2009 年 E92.C 巻 5 号 p.
664-670
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
A data analysis technology of atomic force microscopy for atomically flat silicon surfaces has been developed. Atomically flat silicon surfaces composed of atomic terraces and steps are obtained on (100) orientation 200mm diameter wafers by annealing in pure argon ambience at 1, 200°C for 30 minutes. Atomically flat silicon surfaces are lead to improve the MOS inversion layer mobility and current drivability of MOSFETs and to decrease the fluctuations in electrical characteristics of MOSFETs. It is important to realize the technology that evaluates the flatness and the uniformity of atomically flat silicon surfaces. The off direction angle is calculated by using two straight edge lines selected from measurement data. And the off angle is calculated from average atomic terrace width under assumption that height difference between neighboring terraces is equal to the step height, 0.135nm, of (100) silicon surface. The analyzing of flatness of each terrace can be realized by converting the measurement data using the off direction angle and the off angle. And, the average roughness of each terrace is about 0.017-0.023nm. Therefore, the roughness and the uniformity of each terrace can be evaluated by this proposed technique.
抄録全体を表示
-
Jae-Young PARK, Jong-Kyu SONG, Chang-Soo JANG, San-Hong KIM, Won-Young ...
原稿種別: PAPER
2009 年 E92.C 巻 5 号 p.
671-675
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
The holding voltage of high-voltage devices under the snapback breakdown condition has been known to be much smaller than the power supply voltage. Such characteristics cause high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used as the ESD power clamp circuit. A new latchup-free design of the ESD power clamp circuit with stacked-bipolar devices is proposed and successfully verified in a 0.35µm BCD (Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the power supply voltage.
抄録全体を表示
-
Oh Jun KWON, Kae Dal KWACK
原稿種別: PAPER
2009 年 E92.C 巻 5 号 p.
676-680
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
In this paper, a novel 800mV beta-multiplier reference current source circuit is presented. In order to cope with the narrow input common-mode range of the Opamp in the reference circuit, the resistive voltage divider was employed. High gain Opamp was designed to compensate for the intrinsic low output resistance of the MOS transistors. The proposed reference circuit was designed in a standard 0.18µm CMOS process with nominal
Vth of 420mV and -450mV for n-MOS and p-MOS transistor, respectively. The total power consumption including Opamp is less than 50µW.
抄録全体を表示
-
Oh Jun KWON, Kae Dal KWACK
原稿種別: PAPER
2009 年 E92.C 巻 5 号 p.
681-685
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
A 900mV single-stage class-AB amplifier suitable for the Switched-Opamp technique is presented. To improve the slew-limited characteristics, a Dynamic Current Source (DCS) circuit which boosts the tail currents of the amplifier is proposed. The tail current of the proposed circuit is well defined and independent of technology parameters and supply variations. The tail current of the amplifier is 40µA with zero differential voltages, while the maximum output current is nearly 900µA. A single-loop 3rd order Σ-Δ modulator with the proposed amplifier was designed. For a 260mV 15.625kHz sinusoidal input signal, the simulated dynamic range of the modulator is 89dB.
抄録全体を表示
-
Hideyuki OKITA, Toshiharu MARUI, Shinichi HOSHI, Masanori ITOH, Fumihi ...
原稿種別: PAPER
2009 年 E92.C 巻 5 号 p.
686-690
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
Current collapse phenomenon is a well known obstacle in the AlGaN/GaN HEMTs. In order to improve the surface stability of HEMTs, we have investigated the SiN passivation film deposited by T-CVD, and we found that it improves both gate leakage current and current collapse phenomenon [1]. Moreover, we compared the T-CVD and PE-CVD passivation films, on high electric field DC and RF characteristics. We found that T-CVD SiN passivation film improves
BVds-off by 30% because of the reduction of gate leakage current. It also improved η
d in the output power characteristics by load-pull measurement, which indicates the decrease of the current collapse phenomenon. Also we fabricated a multi-fingered 50W-class AlGaN/GaN HEMT with T-CVD SiN passivation film and achieved 61.2% of high drain efficiency at frequency of 2.14GHz, which was 3.6 points higher than that with PE-CVD SiN passivation film.
抄録全体を表示
-
Hironari CHIKAOKA, Yoichi TAKAKUWA, Kenji SHIOJIMA, Masaaki KUZUHARA
原稿種別: PAPER
2009 年 E92.C 巻 5 号 p.
691-695
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
We have evaluated the tunneling contact resistivity based on numerical calculation of tunneling current density across an AlGaN barrier layer in non-polar AlGaN/GaN heterostructures. In order to reduce the tunneling contact resistivity, we have introduced an n
+-Al
XGa
1-XN layer between an n
+-GaN cap layer and an i-AlGaN barrier layer. The tunneling contact resistivity has been optimized by varying Al composition and donor concentration in n
+-Al
XGa
1-XN. Simulation results show that the tunneling contact resistivity can be improved by as large as 4 orders of magnitude, compared to the standard AlGaN/GaN heterostructure.
抄録全体を表示
-
Takuya NISHIMURA, Nobuhiro MAGOME, HyunChul KANG, Taiichi OTSUJI
原稿種別: PAPER
2009 年 E92.C 巻 5 号 p.
696-701
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
We have proposed a terahertz (THz) emitter utilizing two-dimensional plasmons (2DPs) in a super-grating dual-gate (SGG) high electron mobility transistor (HEMT). The plasmon under each grating gate has a unique feature that its resonant frequency is determined by the plasma-wave velocity over the gate length. Since the drain bias voltage causes a linear potential slope from the source to drain area, the sheet electron densities in periodically distributed 2DP cavities are dispersed. As a result, all the resonant frequencies are dispersed and undesirable spectral broadening occurs. A SGG structure can compensate for the sheet electron density distribution by modulating the grating dimension. The finite difference time domain simulation confirms its spectral narrowing effect. Within a wide detuning range for the gate and drain bias voltages giving a frequency shifting of ±0.5THz from an optimum condition, the SGG structure can preserve the spectral narrowing effect.
抄録全体を表示
-
Hyeok Jun SON, Il Woong KWON, Yong Soo LEE, Hee Chul LEE
原稿種別: PAPER
2009 年 E92.C 巻 5 号 p.
702-707
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
In this paper, Poly(3, 4-ethylenedioxythiophene): Poly (Styrenesulfonate) (PEDOT: PSS) thin films for application in a bolometer, a type of uncooled infrared image sensor, are presented. In addition, the TCR and 1/ƒ noise dependencies of PEDOT: PSS thin films on the thermal treatment conditions are demonstrated. It is also shown that an appropriate thermal treatment can suppress the 1/ƒ-> noise of PEDOT: PSS thin films while maintaining the resistivity and TCR. A high TCR value over -4%/°C (within 10ohm·cm) through chemical treatment is also presented. The results of this study show that PEDOT: PSS thin films have potential for use as a bolometric material.
抄録全体を表示
-
Dong-Heon HA, Chi Ho HWANG, Yong Soo LEE, Hee Chul LEE
原稿種別: PAPER
2009 年 E92.C 巻 5 号 p.
708-712
発行日: 2009/05/01
公開日: 2009/05/01
ジャーナル
認証あり
A new readout integrated circuit is developed for application in an amorphous silicon-based microbolometer array with a pixel pitch of 35µm. The proposed circuit lowers the power dissipation for a pixel-level analog-to-digital converter (ADC), which uses a comparator and a counter for its data conversion. The infrared current of a microbolometer is proportional to the resistivity changes of the microbolometer. Thus, the required number of counter operations for the pixel ADC can be determined according to the microbolometer current variation. The counting number precisely determines how much infrared flux is absorbed. A 14bit counter should normally be used for the pixel ADC for this kind of operation. However, when the proposed current skimming scheme is adopted, the total bits for the counter in the pixel ADC can be reduced to 12bits. Due to the proposed mechanism, the required operational speed of the comparator can lower than that of a conventional circuit. Consequently, the overall power dissipation in the comparator and counter is less than that of a conventional structure. This low power approach is very suitable in the pixel-level ADCs of microbolometers.
抄録全体を表示