This review provides a current overview of the fabrication processes for superconducting digital circuits at CRAVITY (clean room for analog and digital superconductivity) at the National Institute of Advanced Industrial Science and Technology (AIST), Japan. CRAVITY routinely fabricates superconducting digital circuits using three types of fabrication processes and supplies several thousand chips to its collaborators each year. Researchers at CRAVITY have focused on improving the controllability and uniformity of device parameters and the reliability, which means reducing defects. These three aspects are important for the correct operation of large-scale digital circuits. The current technologies used at CRAVITY permit ±10% controllability over the critical current density (J_c) of Josephson junctions (JJs) with respect to the design values, while the critical current (I_c) uniformity is within 1σ=2% for JJs with areas exceeding 1.0 µm² and the defect density is on the order of one defect for every 100,000 JJs.

This paper describes the development of superconductor-insulator-superconductor (SIS) mixers for the Atacama Large Millimeter/submillimeter Array (ALMA) from the device point of view. During the construction phase of ALMA, the National Astronomical Observatory of Japan (NAOJ) successfully fabricated SIS mixers to meet the stringent ALMA noise temperature requirements of less than 230 K (5 times the quantum noise) for Band 10 (787-950 GHz) in collaboration with the National Institute of Information and Communications Technology. Band 10 covers the highest frequency band of ALMA and is recognized as the most difficult band in terms of superconducting technology. After the construction, the NAOJ began development studies for ALMA enhancement such as wideband and multibeam SIS mixers according to top-level science requirements, which are also presented.

We review a new superconducting element, called “magnetic Josephson junctions” with a magnetic barrier instead of the insulating barrier of conventional Josephson junctions. We classify the three types of magnetic barrier, i.e., diluted alloy, conventional ferromagnet, and magnetic multilayer barriers, and introduce various new physics such as the π-state arising in magnetic Josephson junctions due to the interaction between superconductivity and magnetism.

One of the highest performing single-photon detectors in the visible and near-infrared regions is the superconducting nanostrip photon detector (SNSPD or SSPD), which usually uses NbN or NbTiN as the superconductor. Using other superconductors may significantly improve, for example, the operating temperature and count rate characteristics. This paper briefly reviews the current state of the potential, characteristics, thin film growth, and nanofabrication process of SNSPD using various superconductors.

We developed a Nb 4-layer process for fabricating superconducting integrated circuits that involves using caldera planarization to increase the flexibility and reliability of the fabrication process. We call this process the planarized high-speed standard process (PHSTP). Planarization enables us to flexibly adjust most of the Nb and SiO₂ film thicknesses; we can select reduced film thicknesses to obtain larger mutual coupling depending on the application. It also reduces the risk of intra-layer shorts due to etching residues at the step-edge regions. We describe the detailed process flows of the planarization for the Josephson junction layer and the evaluation of devices fabricated with PHSTP. The results indicated no short defects or degradation in junction characteristics and good agreement between designed and measured inductances and resistances. We also developed single-flux-quantum (SFQ) and adiabatic quantum-flux-parametron (AQFP) logic cell libraries and tested circuits fabricated with PHSTP. We found that the designed circuits operated correctly. The SFQ shift-registers fabricated using PHSTP showed a high yield. Numerical simulation results indicate that the AQFP gates with increased mutual coupling by the planarized layer structure increase the maximum interconnect length between gates.

The microfabrication technique based on synchrotron radiation (SR) direct etching process has recently been applied to construct PTFE microstructures. This paper proposes a PTFE substrate integrated waveguide (PTFE SIW). It is expected that the PTFE SIW contributes to the improvement of the structural strength. A rectangular through-hole is introduced taking the advantage of the SR direct etching process. First, a PTFE SIW for the Q-band is designed. Then, a cruciform 3-dB directional coupler consisting of the PTFE SIW is designed and fabricated by the SR direct etching process. The validity of the PTFE SIW coupler is confirmed by measuring the frequency characteristics of the S-parameters. The mechanical strength of the PTFE SIW and the peeling strength of its Au film are also additionally investigated.

In order to upgrade the refresh rate about High-Resolution (1280×1024) OLED-on-Silicon (OLEDoS) microdisplay, this paper discusses one compression scan strategy by reducing scan time redundancy. This scan strategy firstly compresses the low-bit gray level scan serial as one unit; second, the scan unit is embedded into the high-bit gray level serial and new scan sequence is generated. Furthermore, micro-display platform is designed to verify the scan strategy performance. The experiment shows that this scan strategy can deal with 144Hz refresh rate, which is obviously faster than the traditional scan strategy.

Frequency delta sigma modulation (FDSM) is a unique analog to digital conversion technique featuring large dynamic range with wide frequency band width. It can be used for high performance digital-output sensors, if the oscillator in the FDSM is replaced by a variable frequency oscillator whose frequency depends on a certain external physical quantity. One of the most important parameters governing the performance of these sensors is a phase noise of the oscillator. The phase noise is an essential error source in the FDSM, and it is quite important for this type of sensors because they use a high frequency oscillator and an extremely large oversampling ratio. In this paper, we will discuss the quantitative effects of the phase noise on the FDSM output on the basis of a simple model. The model was validated with experiments for three types of oscillators.

This letter proposes a power amplifier (PA) with compact matching network. This structure is a parallel dual radial microstrip line in the output matching network branch. The input impedance expression based on the structure is deduced through theoretical analysis, and the load impedance that satisfies the class EFJ PA is obtained through the impedance expression. Compared with the traditional design method, this design method is simple and novel, and the structure is more compact. In order to further improve efficiency and expand bandwidth, the input matching network adopts a stepped impedance matching method. In order to verify the correctness of the design, a broadband high-efficiency PA was designed using GaN HEMT CGH40010F. The test results show that the drain efficiency is 61%-71% in the frequency band 1.4-3.8GHz, the saturated output power is 40.3-41.8dBm, and the size is 53×47mm².