Journal of The Japan Institute of Electronics Packaging
Online ISSN : 1884-121X
Print ISSN : 1343-9677
ISSN-L : 1343-9677
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Volume 17, Issue 5
Displaying 1-29 of 29 articles from this issue
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Preface
Special Articles / Front Line of Device Embedded Substrate and Peripheral Technologies
Trends and Anticipation of Device Embedding
Brand-New Device Embedding Technologies
Materials and Designing
Jisso and Inspection Technologies
Technical Paper
  • Room Temperature Bonding of Wafers Using Au Films with Various Holding Times in Air
    Hitoe Kon, Miyuki Uomoto, Takehito Shimatsu
    2014 Volume 17 Issue 5 Pages 431-435
    Published: 2014
    Released on J-STAGE: November 08, 2014
    DOIhttps://doi.org/10.5104/jiep.17.431
    JOURNAL FREE ACCESS
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    The bonding of two flat wafers using nanocrystalline Au films is a promising process to achieve wafer bonding at room temperature in air. In this study, we kept wafers in air after Au-film deposition on the wafer surfaces. Bonding was then performed after exposure time texp. Quartz glass wafers were bonded using Au films (3, 7, and 20 nm thick) with Ti underlayers. The bonding strength was assessed as a function of texp and film thickness. TEM images revealed that the recrystallization of Au atoms at the Au-Au bonded interface occurs at room temperature, even with texp = 168 h (1 week). The bonding energy tended to decrease as the Au film thickness decreased, but the bonding energy was greater than the Au film surface energy (=1.63 J/m2) even with 3 nm Au films in the texp range up to 1 week, indicating that the bonding process is highly reliable.
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  • Patterning on the Arbitrary Surface for the Development of 3D Photomask
    Masahiro Hayashi, Yi Zhang, Hideki Takagi, Masanori Hayase, Ryutaro Ma ...
    2014 Volume 17 Issue 5 Pages 436-441
    Published: 2014
    Released on J-STAGE: November 08, 2014
    DOIhttps://doi.org/10.5104/jiep.17.436
    JOURNAL FREE ACCESS
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    Micro-patterning on non-planar surfaces is required in the packaging and MEMS fields in order to fabricate new micromechanical devices. In this paper, we propose a new patterning process using a 3D photolithography technique for micro-patterning on a non-planar surface. We also report on the fabrication of a 3D photomask for a substrate using the proposed process. The patterning process is based on a two-photon polymerization laser-writing and lift-off process. We confirmed that fine patterns with line widths down to 2 μm were successfully formed inside the semi-circular trench. In addition, the transfer of the micro-pattern from the 3D photomask to the cylindrical surface of the fiber substrate was confirmed.
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Short Note
  • Bath Control Technique by Electrowinning of Copper Ion Impurities in the Process of Gold Plating
    Kazuhiro Date, Sachio Yoshihara, Junichi Nozawa, Naokatsu Nojiri
    2014 Volume 17 Issue 5 Pages 442-444
    Published: 2014
    Released on J-STAGE: November 08, 2014
    DOIhttps://doi.org/10.5104/jiep.17.442
    JOURNAL FREE ACCESS
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    There are so-called wire bonding methods to electrically connect semiconductor IC chips and printed wiring boards. Typically, gold plating is applied to the connection terminal pad on the wiring board, and the higher the purity of the plated gold film, the higher the connection strength of the wire and the better the long term reliability. But in the process of manufacturing printed wiring boards, it is impossible to completely avoid impurities in the plating bath. In this study, we removed impurities in the gold plating bath using constant potential electrolysis at several different electrode potentials, and we discuss the performance of this technique for the removal of impurities in the gold plating bath.
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