Journal of The Japan Institute of Electronics Packaging
Online ISSN : 1884-121X
Print ISSN : 1343-9677
ISSN-L : 1343-9677
Volume 20, Issue 6
Displaying 1-20 of 20 articles from this issue
Preface
Special Articles / Heterogeneous Integration
2016 JIEP Award-Technical Development
  • Kouichi Tanaka, Yoshihiro Machida, Atsushi Nakamura, Masato Umehara, T ...
    2017Volume 20Issue 6 Pages 418-424
    Published: 2017
    Released on J-STAGE: September 01, 2017
    JOURNAL FREE ACCESS
    Along with miniaturization of mobile devices, the PoP (Package on Package) structure has been adopted for high-density 3D packaging. However, the conventional PoP structure using FC-BGA (Flip Chip-BGA) has some issues regarding package warpage and thickness. To resolve these issues, we have developed an embedded device package named MCeP® (Molded Core embedded Package) for the bottom package of the PoP structure. MCeP® consists of a top substrate, a bottom substrate and an embedded layer in which the IC device is encapsulated by molding resin. This package has the beneficial characteristic of reducing package warpage. It is possible to control package warpage by optimizing the thickness and material of each layer (top substrate, bottom substrate and embedded layer).
    In this paper, we describe the MCeP® structure, process flow and simulation, as well as measurements of package warpage when changing the thickness of each layer and the CTE (Coefficient of Thermal Expansion) of the substrate.
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