[in Japanese]

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With the rapidly growing volume of communication traffic, the capacities of routers and servers in data centers have had to increase to an extraordinary extent. As part of this, active optical cables (AOCs) have been employed to realize very-high-speed signal transmission in rack-to-rack applications over several tens of meters, instead of conventional electrical wiring using coaxial cables, and the market for AOCs has been growing rapidly. On the other hand, next generation high-density optical interconnects tend to employ an architecture of mounting parallel optical modules on a PCB. The market for these high-density optical interconnects is expected to grow significantly over the next several years. In order to meet the requirements of mounting architectures in both applications, we have developed parallel-optical modules which can be mounted using a solder-in-reflow process and can also be replaced through an electrical-pluggable interface. Furthermore, we propose 1060-nm VCSEL-based optical interconnects whose benefits include high speed, high reliability, and lower power consumption. We also demonstrate their benefit in optical link performance. The power consumption of an optical link is as low as 6.4 mW/Gbit/s over the operating temperature. In an effort to verify this with actual systems, we solder-mounted 1060-nm 10Gbit/s×12-channel parallel-optical modules and also performed full reliability tests. From these, we confirmed good results in all tests and concluded the optical modules are applicable to actual applications.

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The K computer ranked first on the TOP500 List of June 2011. The achievement of such high performance is due not only to the high-performance CPUs but also largely to the system packaging technologies: rack technology to allow high-density mounting of the CPUs, connection technology to achieve high-speed data transmission between the CPUs, and cooling technology for improved reliability. This paper describes the printed wiring board technologies applied to the K computer.

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In recent years, PCI Express and USB have become established as high-speed serial transmission methods, reaching speeds of 5–10 Gbps and showing remarkable progress. As a result, several new design techniques for high-speed digital circuits have been recommended for printed circuit boards (PCB) by device makers. However, in order to adopt the actual designs, it is necessary to grasp their effects and detailed mechanisms. We focused on a technology which removes the copper on the ground plane beneath the chip component pad, and verified the effect. Design methods corresponding to the layer constitution and the material of the printed circuit board are proposed. The S-parameter, current distribution, and emission characteristics are analyzed by means of an electromagnetic field analysis simulator (Sonnet EM) of the method-of-moment. In addition, the S-parameter of the test board was measured and the effect was verified.

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In recent years, in an effort to prevent global warming and to achieve energy saving, power modules have become common not only in transport equipment but also in home electronics. In these semiconductor packages, large-scale ceramic substrates are bonded on copper heat sinks to control high voltages and high currents. In this paper, we report on a new experimentally developed bonding process realizing void reduction in solder joints. A ceramic substrate having high-temperature solder bumps on slit pads was mounted on a heat sink printed with low-temperature solder paste. The solder bumps are then reflowed. As a result, the solder joints have fewer voids than conventional methods. Moreover, the mechanism of void extinction is revealed using X-ray dynamic observation.

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Femtosecond lasers can be used for forming a nano-sized periodic structure on the surface of fused silica. However, the processing control range is narrow and unstable due to the nonlinearity of the multiphoton absorption process. By coating the surface with a thin metallic film, we found that the periodic structure can be formed easily below the ordinary ablation threshold for fused silica. However, the periodic structure processing mechanism was not understood. We proved that the metallic nano-sized particles on the fused silica contributed to the nano-sized structure formation, and confirmed that the nano-sized structure could be formed even with laser processing of only one pulse. Furthermore, the depth of the nano-sized periodic structure depends on the volume of the metallic nano-sized particles.

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This paper presents a practical method of drift-diffusion device simulation in order to evaluate the effects of mechanical stress on n-type silicon semiconductor devices. The device simulation incorporates an electron mobility model for considering the effects of mechanical stress. In our previous study, the changes in relative populations and momentum relaxation times (intervalley scattering) of electrons in conduction-band valleys were modeled in the electron mobility model. In this study, we added modeling of the change in the effective mass of electrons as a means of considering the effects of uniaxial stress. Stress-induced variations of electrical characteristics on nMOSFETs are evaluated using a device simulation including the proposed electron mobility model. Then, the electron mobility model and the simulation method are verified by comparing them with experimental results. It is demonstrated that experimental results can be reasonably estimated using this simulation method. In other words, the device simulation including the proposed electron mobility model can determine the uniaxial-load-direction dependence of the stress sensitivity of the change in electrical characteristics. To improve the accuracy of our simulation method, necessary improvements in the electron mobility model are identified.

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