CSP (Chip Scale Package) and/or FCA (Flip Chip Attach) are becoming the important new high-density packaging technology for the consumer electric products. In addition, the use of build-up boards for mounting the packages has been tried. However, the reliability of the solder connection depends on the structure of the package, the motherboard, and the material properties. In this paper, the solder connection reliability for CSP and FCA packages, mounted on the build-up board, is assessed. The results based on optimizing each of the parameters are reported. The most reliable packaging design and a compact FEM (Finite Element Method) model for the reliability assessment are suggested. The verification of the numerical analysis results using tests on the actual hardware is also shown. On these results, this FEM model is applied to the reliability assessment of MCM with the evaluation of the warpage and Encapsulant volume.

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Moiré interferometry technique was adopted to analyze thermal deformations of four kinds of flip-chip devices mounted on FR-4 substrate and multi-layer substrate, with and without underfill. A thermal loading was applied by heating the devices from room temperature 25°C to an elevated temperature 100°C. The experimental results showed that the underfill gave similar curvatures of silicon chip and the substrate. In the flip-chip devices mounted on the multi-layer substrate, thermal expansion coefficient mismatch between the chip and substrate was reduced, and bending deformations were decreased. The deformation of solder balls in the underfilled flip-chip device mounted on the multi-layer substrate was the least in the four kinds of flip-chip devices.

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Thermal residual stress and warp deformation behavior generate in an electronic device composed of LSI chip and adhesive, FR-4 substrate were analyzed, using the numerical simulation method based on the linear vscoelastic theory. The interfacial thermal stress and warp deformation of laminated beam composed of LSI chip and adhesive are larger than that of LSI chip and FR-4 substrate. It was clarified that thermal residual stress and warp deformation generate in an electronic device are strongly influenced by the loaded temperature conditions as well as material properties.

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The interfacial reaction between Sn-Zn solders and Cu in solid-state was examined. The microstructure change of the solders due to heat-exposure at 125°C, 135°C, and 150°C was also examined. In case of Sn-8Zn-3Bi and Sn-9Zn/Cu joints, the Cu-Zn intermetallic compounds at the interface grow by following the parabolic law at initial stage, by the heat-exposure. Much amount of Cu diffuses into the solder layer resulting in the formation of Cu₅Zn₈ grains. The speed of the phase transformation of Zn phase into Cu₅Zn₈ of the Sn-8Zn-3Bi/Cu reaction system is higher than that in the Sn-9Zn/Cu system at all temperatures. The voids are found at the solder/reaction layer interface in long time heat-exposure. The Sn-Cu compound and Sn phase which is with a small amount of Zn and Bi are observed at the interface of reaction layer and Cu. On the other hand, Sn-20Zn and Sn-30Zn/Cu joints not to form large voids at interface and can maintain good stability against heat-exposure.

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Copper Damascene via bottom accelerating additives was investigated by patterned cathode of cathode only at trench bottom. The cathodic current on a patterned trench bottom cathode increases with SPS in addition to Cl^-, PEG and JGB. This current also increases with increase of SPS concentration. This accelerating effect of SPS has been found with typical combination of four additives (Cl^-+PEG+JGB+SPS) used for via filling. The cathodic current increases with increase of aspect ratio of patterned cathode. With higher aspect ratio of deeper trench, the trench bottom accelerating substance is considered to accumulated at trench bottom. This substance is related to SPS. From the cross section observation of deposit thickness, this trench bottom accelerating substance is considered to be formed during electrolysis. This accumulates at trench of deeper trench during electrolysis. SPS decomposes into monomer by electrolysis and this may accumulates at trench bottom and increases the trench bottom current.

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We have developed a new de-coupling capacitor, which is contained a small value of dumping resister. The capacitor is effective to compress impedance increase at an anti-resonance frequency when they are connected parallel to widening their low impedance range. It has been confirmed with experimental measurement, the radiated noise is reduced by the capacitors at the anti-resonance frequencies.

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As for the inside analysis of a semiconductor device, we observed the wire sweep of plastic package by a newly developed X-ray CT instrument. We could observe the three-directional configuration of the bonding wire of encapsulated QFP by composing two-dimensional cross section CT scan image. By this new method, we got more smooth wire profiles than the result we observed before.

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Center humped bump is ideal shape for high density interconnection. This is because of smaller interconnection area and less lateral expansion in thermal compression. Coumarin additive was found to show inhibition effect and diffusion control from current-potential curves with rotation disk electrode. The two layered photo resist structure was newly introduced. With two layered resist structure and Coumarin, we succeeded in forming center humped bumps. The center humped bump has aspect ratio of 0.6 having 12μm height and 20μm diameter.

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A stacked device called SEP (System Embedded Package) was developed to drastically increase LSI density relative to its area on the circuit board. This was achieved by fabricating an LSI package in a stacked structure. This device has been applied to mobile communication equipment. The bottom-side chip was made into a flip-chip structure and attached to the substrate by the NSD method, which involves the use of stud-bumps and adhesive encapsulation film. On the top of this flip-chip LSI, another LSI was stacked and interconnected by using low-profile wire-bonding technology. The use of flip-chip bonding for the bottom-side LSI permitted easy wire bonding on the topside LSI. Furthermore, this packaging technology was able to provide a super multi-pin system LSI with more than 600 pins. By adopting this package in a mobile communication product, the required package area on the circuit board could be reduced by 35%.

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