The core resin film, electrode configuration and processing technology of a SrTiO₃ (STO) thin-film capacitor, which is expected to be suitable for fabrication at reduced costs, were examined. The high-frequency characteristics of the capacitor fabricated using this processing technology were also investigated. The following results were obtained. (1) Fabrication of an STO thin-film capacitor on a polyimide or glass-epoxy film is possible. (2) A Ru/STO/Cr–Cu three-layer-film configuration is highly promising. (3) Batch processing of the pattern formation of the 300-nm-thick STO thin-film capacitor by all chemical-etching techniques is possible. In addition, it was confirmed that the STO thin-film capacitor has a flat-frequency response up to 10 GHz, a relative dielectric constant of 17 and a capacitor density of 500 pF/mm².

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The residual stress in LSI chips mounted in synchronous stacked bump structures such as stacked memory structures varies drastically depending on their bump joint structures. It sometimes reaches a few hundred MPa and deteriorates their functions and the reliability of products. Thus, a new bump joint structure is proposed for minimizing the residual stress considering the relative positions between bumps and vias using a finite element analysis. The amplitude of the residual stress in each stacked chip in the optimum stacked structure can be decreased to less than 30 MPa and the difference of the residual stress between the stacked chips to nearly 0 MPa. The alternative alignment structure between bumps and vias is effective for minimizing the local residual stress in a chip. Introducing a stress-relaxation layer under the bump using a material with a low elastic modulus is also effective for minimizing the local residual stress. Therefore, it is important to optimize the assembly structure of the three-dimensionally stacked LSI chips in order to minimize the residual stress.

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We have developed a dedicated device for sealing characterization using the SCREAM method by which the pressure in a sealed micro-cavity can be measured. We also newly propose a method for estimating the air damping of resonators in the free-molecule regime. Although a great deal of research sealing has been carried out using resonators or diaphragms for the sealing characterization, there are problems such as an insufficient measurable pressure range. This paper shows that the necessary minimum measurable pressure is 0.1 Pa and a suitable sensing method for the characterization is a resonant type sensor using pressure dependence of the quality factor of a resonator. The sealing characterization device with a measurable pressure range of 0.1–10³ Pa was successfully developed.

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We investigate the effects of the surface profiles of Au thin films on room temperature vacuum sealing by a simulation using surface profiles measured with an AFM. Vacuum sealing is necessary for some MEMS devices. If the vacuum seal-bonding is carried out at room temperature, then it can be applied to diverse combinations of materials. In a previous study, we found the surface activated bonding method can be applied to vacuum sealing. However a detailed analysis of as-sputtered films for the method has not been studied. We investigate the influence of the surface profiles on necessary contact ratios and leak rates

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We have developed a CoC (Chip-on-Chip) packaging technology for high-reliability applications. Gold-to-Gold interconnects with Au stud bumps and plated Au bumps were used for the new technology. EBSP (Electron Backscatter Diffraction Patterns) were observed to estimate the Au–Au bond formation mechanism, and the plasma treatment effect on the Au bump surface was clarified using AFM (Atomic Force Microscopy) and ESCA (Electron Spectroscopy for Chemical Analysis). Furthermore, we have investigated the mechanical damage and the influences on device characteristics of CoC interconnection processes using test chips with under-pad multi-layer wiring and transistors. Finally, we fabricated CoC structure packages including a single chip microcomputer and a memory chip, and successfully confirmed their excellent reliability.

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It is widely known that the use of insoluble anodes result in a greater quantity of additive consumption than phosphorised copper anodes. Consequently, the insoluble anode is covered with a permeable membrane in use, but recently, insoluble anodes that do not cause considerable additive consumption without permeable membrane have been reported. This paper reports on the result of our study on the cause of substantial additive consumption that results from the use of insoluble anodes. As a result of the study, it is clearly suggested that in the acid copper plating bath containing chloride ions, hypochlorite is generated at the surface of the insoluble anode by the chloride oxidation reaction, and the hypochlorite decompose the additives by oxidation.

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