[in Japanese]

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The high-precision flip-chip bonding technologies in 20μm pitch are applied to connect the copper plugs through the Si devices with the micro bumps formed on the each copper plug for 3D LSI. Generally, it is said that the ultrasonic flip-chip bonding (UFB) technologies are preferable bonding process as the interconnections at low profile and low temperature. In this paper, the possibilities of hyperfine interconnections utilizing electroplated Au bumps in 20μm-pitch are discussed on the chip on chip (COC) structure as feasibilities. First, the basic bondabilities on the sputtered Au film were evaluated. The effect of the ultrasonic and the sputter cleaning of the bump surface were confirmed. Secondly, the possibilities of the micro-joints were confirmed on the electroless nickel and the gold (Ni/Au) plated film as the result of the evaluation on the tensile strength. At last, the possibilities of the interconnections utilizing UFB in 20μm-pitch between the electroplated gold bumps and the electroless Ni/Au plated bumps were found out at the cross-section. The all achievement of the basic studies on the packaging process will realize the 3D LSI in the near future, which is proud of the scalabilities and the higher-performance. The subjects are the selection of the optimized process conditions and the establishment of the micro-joint reliabilities utilizing UFB process.

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In the field of optical module assemblies, there is a demand for the passive alignment method, which is considered to contribute both to the cost reduction and the throughput enhancement. Although the optical modules require submicron level bonding accuracy, the conventional bonders can offer no better than ±5μm level accuracy.In this paper, upgrading technologies for passive alignment bonder are reported, i.e. enhanced recognition accuracy of fiducial marks which are placedon the electrode surfaces of LD chips and silicon substrate respectively, anti-vibration structures, and anti-thermal expansion solutions. On the third issue, particularly, a new calibration method has been developed to compensate the thermal expansion that causes 1μm positional shifting at 1°C temperature change in the atmosphere or of the machine. Verification of test results on mounting accuracy is also reported.

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The copper foil crystals have been found to grow with lateral growth of macrosteps on the (100) surface of the f.c.c. structure. The copper foil crystals with geratin additive have the (111) orientation and have triangular pyramidal morphology. With chloride only and geratin and chloride, the crystals have (110) orientation and pyramidal morphology. Both of these crystals grow with the lateral growth of macrosteps on the (100) surface. The cross sections and the surface roughness have been successfully explained by our proposed crystal growth mechanism of macrostep lateral growth on the (100) surfaces and the crystal orientations of (111) and (110) .

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The influence of the heat after wire bonding on the separability between Au wire and Ag plating on Cu alloy substrate has been investigated, and the position that introduces the separation technique of bonding wire into the packaging process of CSP is examined. Bonding strength decreases with decrease in the bonding temperature and bonding strength and contact area have a linear relation. Furthermore, when heat treatment is performed after wire bonding, the strength tends to saturate after increasing, and the separability in the bonding area bars from an early stage. Based on the above results, wire bonding should be done at temperature as low as possible in the packaging process of CSP, a substrate should be peeled off making wires separable just before the post cure.

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A drop test was performed to test the reliability of ball-type solder joints used in semiconductor packages. The maximum surface strain of a Printed Wiring Board (PWB), on which a Ball Grid Array (BGA) package was mounted, was a key parameter for estimating the life of solder joints reliability. The effects of the thickness of the PWB and the falling direction on the life of the solder joints were evaluated using the surface strain. The life of the solder joints can be estimated using the surface strain of a PWB, and the life increased as the strain decreased. The reliability of Sn-37Pb solder used for ball joints of fan-out type packages was higher than that of Pb free solder.

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Thermal residual stress and warp deformation behavior generate in electronic devices which are composed of different materials, such as LSI chip, metal, adhesive and FR-4 substrate were analyzed, using the thermo-viscoelastic numerical simulation based on the linear viscoelastic theory. It was clarified that thermal residual stress and warp deformation behavior were influenced by not only a thickness of constructive materials but also heat conditions loaded to the devices, and that there was a combination of layer construction which had maximum thermal residual stress.

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By suddenly expansion of the internet communications, signal capacity of communication systems has grown rapidly and the speed of each IC using in the communication systems has been faster, and then the power density of the IC has become lager. On the other hand, the assemble density of IC has been rapidly increased, for example, in the WDM communication systems. So the thermal dissipation performance of the package has become more important. We developed a new concept metal base package using CVD diamond, which has the highest thermal conductivity of all materials, for the 10 Gbps EA driver IC. This IC is one of the most power consumption and highest speed using the light communication. Although the FET temperature of the diamond package reduce to the same as that of a conventional package, we could the size of the diamond package could decreased by 60% in comparison with that of a conventional package. We also ensured that the electrical performance of the diamond package was equivalent to that of the conventional package.

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