A key issue in using alternative lead-free solder is the evaluation of long-term reliability, such as thermal fatigue. In this paper, an estimation method for the thermal fatigue of Sn-Ag-Cu lead-free solder joints using an inelastic constitutive model was studied. First, the mechanical properties of Sn-Ag-Cu lead-free solders were investigated in order to model the inelastic constitutive equation for finite element analysis. Tensile tests and constant load creep tests were carried out. Next, an inelastic constitutive model was investigated. In the modeling, the inelastic strain rate was decomposed into the steady-state part depending on applied stress and the transient part driven by the difference between applied stress and back stress. Finally, in order to investigate the applicability of the proposed constitutive model for Sn-Ag-Cu lead-free solder, finite element analysis was carried out for the solder joints in a quad flat package. The estimation for the fatigue crack initiation was in good agreement with the actual thermal cycle tests for the quad flat package.

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In this paper, we present theoretical and experimental studies of the effect of resonant modes excited inside rectangular cavities formed by ground plates and ground via fences of shielding in a multilayer printed circuit board (PCB) on the electrical performance of via transitions at frequencies up to 10GHz. Three types of the transitions, such as single signal via, signal via surrounded by ground vias to form a vertical wave guiding structure and via pairs for differential signaling, embedded within the boundaries of the shielding in the same PCB are considered. Presented results cover reflection, transmission, and crosstalk phenomena in these types of via transitions under the effect of the cavity modes. As an outcome, some ways to develop interconnect circuits including via transitions embedded in multilayer PCBs at higher frequencies are traced here.

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Uniformity of copper thickness is a critical factor when etching fine conductors in most advanced build up PCBs. A method to achieve good uniformity in pattern plating is discussed. The BGA pattern was divided into small areas and active area densities were defined for each area. The current distribution on the BGA pattern was numerically simulated by solving Laplace and Butler-Voltmer equations. This simulation method seems to be useful to estimate the current density distribution depending on factors such as pattern density and the conductivity of the plating solution. We found that, by placing auxiliary convexities at the edges of each BGA pattern, the auxiliary convexities absorb current which tends to concentrate at the sparsely dispersed pattern. This pattern is generally situated near the edge of the BGA piece, so with the auxiliary convexities, the concentrated current of the sparsely dispersed pattern near the edge of the BGA decreases. The current distribution is changed by the position (distance, height) of the auxiliary convexities. A minimum error of 3.37% was achieved when the position of the auxiliary convexities was optimized.

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It is well known that liquid crystal polymer (LCP) films exhibit excellent mechanical and physical characteristics compared with those of other polymers. In order to apply LCP films on printed circuit boards, the etching conditions required for LCP film to obtain a good anchor effect for electroless copper plating was studied. After etching the LCP film in a 10M KOH solution at 70 degrees for 60-90 minutes, we obtained a copper film with excellent adhesion strength using a plating bath having slow plating speed or using sodium phosphinate as a reducing agent.

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In multi-layer printed circuit boards, many through-holes and via-holes coexist for electrical connection. This paper considers the three dimensional shape measurement of a via-hole and its environmental surface by using a laser displacement meter. The dispersion of the obtained data is caused by the affection of measuring surface. We make smoothing of the measurement data by the two methods of moving average and polynomial approximation. The usefulness of our approach is verified by experiment results.

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We have developed a new technology for thinning optical devices for an opto-electronic interconnection module using an epitaxial lift-off (ELO) technique. The thinned optical devices were fabricated by a process of delaminating the GaAs substrate, selectively etching an AlGaAs release layer between the substrate and epitaxial layers with vertical cavity surface emitting lasers (VCSELs) . Before delaminating the substrate, we fabricated a deep hole in the substrate to enable light emission at a wavelength of 850 nm through the hole. The fabricated 10-μm-thick VCSELs were mounted and soldered at three electrode positions on the dummy glass substrate using AuSn bumping metal, and showed almost the same opto-electronic characteristics before and after ELO, as well as stable DC performance during continuous operation of up to 1000 hours.

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