Journal of The Japan Institute of Electronics Packaging
Online ISSN : 1884-121X
Print ISSN : 1343-9677
ISSN-L : 1343-9677
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Volume 18, Issue 3
Displaying 1-15 of 15 articles from this issue
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Preface
Special Articles / Latest Trends in 2.1D/2.5D IC Packaging Technologies
Technical Paper
  • Power Mosfet’s Thermal Resistance Measures Different Value between Body-Diode and Saturate Test Conditions
    Yafei Luo, Yasushi Kajita, Tomoyuki Hatakeyama, Shinji Nakagawa, Masar ...
    2015 Volume 18 Issue 3 Pages 161-166
    Published: 2015
    Released on J-STAGE: August 01, 2015
    DOIhttps://doi.org/10.5104/jiep.18.161
    JOURNAL FREE ACCESS
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    The distribution of heat flux in power MOSFET package is significantly affected by the effective heating area of MOSFET chip. Under different operation conditions, power consumption distribution changes due to MOSFET’s different temperature sensitive parameter. As the result, in cases when MOSFET works in saturation mode (Vth < Vgs < Vth+Vds) and Body-Diode mode, different transient thermal response is usually measured. This article studies thermal resistance change and gives numerical result based on thermal transient test on a popular commercial MOSFET packages. CFD simulation model calibration is also used to visualize heat flux distribution inside package and discuss how it affects package’s thermal characteristics.
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  • Investigation of Microprocessor Heat Conduction Paths by Utilizing One-Dimensional Thermal Network
    Koji Nishi, Tomoyuki Hatakeyama, Shinji Nakagawa, Masaru Ishizuka
    2015 Volume 18 Issue 3 Pages 167-178
    Published: 2015
    Released on J-STAGE: August 01, 2015
    DOIhttps://doi.org/10.5104/jiep.18.167
    JOURNAL FREE ACCESS
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    This paper explores and discusses heat transfer paths of microprocessors in electronic equipment such as PCs (Personal Computers) and tablet devices utilizing a one-dimensional thermal network. Three-dimensional steady state heat conduction simulations are also conducted with different cooling solutions, motherboard sizes, and heat flux distributions at the microprocessors’ silicon die bottoms. After that, thermal resistance values defined in the one-dimensional thermal network with average temperature nodes are calculated and the variation of each thermal resistance with the given conditions is discussed. This paper also discusses the prediction accuracy of the two-resistor model and tries to explain the reasons for its prediction errors. It is found that thermal local resistance and thermal spreading resistances vary with condition differences and the variations result in differences in the microprocessor’s hot spot temperature.
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