The Super High Definition (SHD) image provides the spatial resolution equivalent to 85mm film and the temporal resolution without flicker for the next generation imaging system. This paper describes the SHD image storage and display system, which is designed to display full color motion images with 2048 by 2048 pixels at 60 frames per second progressive for maximum 4 seconds, Firstly, the requirements and the specifications of this system are discussed. Next, the hardware architecture about the installation of 8,000 4M-DRAMs, the high speed data bus, the D/A converter unit, etc. are introduced. In the last, the performance of this system is described.

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We developed a multi-computer type parallel DSP system that offers a peak performance of 15 Gflops. This system is called NOVI-II HiPIPE, and was designed for Super High Definition (SHD) image processing. In order to obtain the great computing power demanded by SHD image processing, a new pipelined vector processor was developed and implemented in each processing element. This pipeline vector processor can achieve 120 Mflops. NOVI-II HiPIPE has 128 mesh connected processing elements and provides 15 GFlops computational power. This paper describes the configuration and performance of NOVI-II HiPIPE.

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This paper describes about a reconfigurable pipeline architecture we proposed, which can satisfy both high-speed and flexible capability. Especially, the effectiveness of the architecture is demonstrated by using many applications of a video-rate image processing system IDATEN (FIVIS/VIP) we developed based on the architecture. Concretely, we classified a word of the motion into three levels, (1) a still eye makes observation of moving objects, (2) a moving eye makes observation of still objects, (3) a moving eye makes observation of moving objects. We show the effectiveness using applications, marathon runner's and golfer's analysis for (1), a active vision robot, a fuzzy controller, and autonomous vehicle for (2), and a dynamic vision system for (3).

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A high speed image processing system has been developed, which is called "SIPS". The first product of SIPS series is named "IMG-1000" which is based on MIMD architecture to provide the performance of 4.5 GOPS. IMG-1000 is devided into three functional blocks. One is TC (Total Controller) to communicate a host computer. Another is FC (Flow Controller) to controle data flow within the system. The other is BP (Basic Processor) to carry out various image processing functions. Moreover programming environment is implemented to support to develope application programs and to do debuging programs. For developing application programs, a compiler and assemblers are provided. For debuging, a trace memory is provided.

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This paper describes realtime processing systems of HDTV signals using parallel processors. An HD-VSP system and an HDTV programmable codec are introduced here. For conventional TV signal processing, a basic parallel processors architecture is already established. In addition to the basic architecture, data rate conversion technique is employed to reduce high sampling rate of HDTV signals. Furthermore, on the HDTV programmable codec, accelerators are combined with parallel processors to realize higher performance. Total performance of the HD-VSP system is 2.5 GOPS and that of the HDTV programmable codec is 15 GOPS at maximum.

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A programmable real-time video signal processing LSI (HD-Picot) has been developed, which has an architecture suitable for the video-rate processing of signals, including both conventional TV and high definition TV. It processes video signals at a speed of 37.125MHz and with 24 bit precision, employing reconfigurable pipeline structure, sophisticated program-control system, and syncronization mechanism between processors. It has two input ports, one output port, two arithmetic logic units, two arithmetic units, two multipliers, two variable delays, and two ports for an external data memory of 2 MBytes. It can calculate address, access (read or write) data memory, and process data simultaneously. The LSI was made with 0.8μm CMOS gate array technology.

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