-
Article type: Cover
1996 Volume 20 Issue 23 Pages
Cover1-
Published: March 19, 1996
Released on J-STAGE: October 13, 2017
RESEARCH REPORT / TECHNICAL REPORT
FREE ACCESS
-
Article type: Index
1996 Volume 20 Issue 23 Pages
Toc1-
Published: March 19, 1996
Released on J-STAGE: October 13, 2017
RESEARCH REPORT / TECHNICAL REPORT
FREE ACCESS
-
M. Yamaguchi, T. Kagawa, T. Yoshikawa, K. Tanaka, T. Sawaya, M. Tsurut ...
Article type: Article
1996 Volume 20 Issue 23 Pages
1-5
Published: March 19, 1996
Released on J-STAGE: October 13, 2017
RESEARCH REPORT / TECHNICAL REPORT
FREE ACCESS
With regard to 8mm Video Camera Recorder, we considered functional blocks allocation for Camera DSP and Video Signal Processing IC, implying common use of some circuits and including circuits used to be external and we organized those ICs operating at 3V voltage supply. As a result, we acbieved epoch-making Hundycam with very low power consumption and low cost.
View full abstract
-
Minoru Arai, Ryuji Kawaguchi, Masahiro Konishi, Kazuki Iwabe
Article type: Article
1996 Volume 20 Issue 23 Pages
7-11
Published: March 19, 1996
Released on J-STAGE: October 13, 2017
RESEARCH REPORT / TECHNICAL REPORT
FREE ACCESS
We have developed 3-CCD High Definition Image Capture Camera using 1.3M-Pixel VT-CCD Image Sensor. Using the movie-mode and vacancy transfer (VT) mode drive of this VT-CCD Image Sensor, we have accomplished automatic control function of this 3-CCD camera.
View full abstract
-
Takeyasu Sakai, Takashi Matsumoto
Article type: Article
1996 Volume 20 Issue 23 Pages
13-18
Published: March 19, 1996
Released on J-STAGE: October 13, 2017
RESEARCH REPORT / TECHNICAL REPORT
FREE ACCESS
A parallel architecture is proposed for fast spatial filtering operations using floating-gate transistors with differential inputs and feedback. All operations are in voltage mode. Only one terminal is required for the feedback which is capable of suppressing the distortions due to active elements. The proposed architecture is also suitable for other operations including DFT. In particular, if DCT is implemented with the proposed architecture together with an array of photosensors, image compression sensor can be realized.
View full abstract
-
T. Satoh, N. Mutoh, M. Furumiya, I. Murakami, S. Suwazono, C. Ogawa, K ...
Article type: Article
1996 Volume 20 Issue 23 Pages
19-23
Published: March 19, 1996
Released on J-STAGE: October 13, 2017
RESEARCH REPORT / TECHNICAL REPORT
FREE ACCESS
We have determined the practical limits of cell size reduction in interline-transfer CCD image sensors, limits resulting from diffraction occurring at the aperture above the photodiode. We have found that image cell size cannot be reduced to a level for which aperture width would fall below about 0.2 μm. We have also found, however, that image cells with greater than 0.2 μm aperture size are sensitive over the entire wavelength range of visible light, and that sensitivity can be increased by thinning the photoshield film.
View full abstract
-
Nobuo Nakamura, Shinji Ohsawa, Yoshiyuki Matsunaga
Article type: Article
1996 Volume 20 Issue 23 Pages
25-30
Published: March 19, 1996
Released on J-STAGE: October 13, 2017
RESEARCH REPORT / TECHNICAL REPORT
FREE ACCESS
-
Keishi Tachikawa, Takuya Umeda, Takao Kuroda
Article type: Article
1996 Volume 20 Issue 23 Pages
31-36
Published: March 19, 1996
Released on J-STAGE: October 13, 2017
RESEARCH REPORT / TECHNICAL REPORT
FREE ACCESS
An automatic simulation system has been developed which analyzes automatically basic electric characteristics of CCD image sensor from a process simulation result. High performance cell technology has been developed by using this system in shorter development period. CCD's dynamic range has been achieved 1.8 times in comparison with the conventional technology. And simulation period has been shortened to about 1/10 to gat rid of complicated repetitious procedures.
View full abstract
-
Tomohisa Ishida, Tadao Isogai, Toshikazu Yoneyama, Masahiro Juen, Tune ...
Article type: Article
1996 Volume 20 Issue 23 Pages
37-42
Published: March 19, 1996
Released on J-STAGE: October 13, 2017
RESEARCH REPORT / TECHNICAL REPORT
FREE ACCESS
We have developed a 1.6M pixel BCAST (Buried Charge Accumulator and Sensing Transistor array) image sensor with a novel pixel structure, which is suitable for a large format, high resolution and high performance image sensor. The pixel design and the operation of this image sensor are explained. The fundamental characteristics-sensitivity of 2V/lx・s, dynamic range of 75dB, noise equivalent exposure of 9.2×10^<-5> lx・s, and dark FPN level of-66dB have been achieved.
View full abstract
-
K. Ishikawa, Y. Matsuda, M. Masuyama, T. Yamada, K. Tachikawe, Y. Miya ...
Article type: Article
1996 Volume 20 Issue 23 Pages
43-48
Published: March 19, 1996
Released on J-STAGE: October 13, 2017
RESEARCH REPORT / TECHNICAL REPORT
FREE ACCESS
A 1/4-inch 330k-Square Pixel Progressive-scan IT-CCD Image Sensor has been developed. This device has a new circuit to achieve the suitable reset condition automatically. The saturation output of 600mV was obtained by 1) the improvement of the doping profile of the vertical CCD under the lower temperature then the conventional process after the formation of VCCD, 2) 4-gates structure and 3) simple pixel structure. One of this device applications was proposed a Hyper-Dynamic range CCD with (4+1) phase driving.
View full abstract
-
Shinichi Murakami, Toshihiro Kawamura, Fumiaki Futamura, Satoshi Uchiy ...
Article type: Article
1996 Volume 20 Issue 23 Pages
49-54
Published: March 19, 1996
Released on J-STAGE: October 13, 2017
RESEARCH REPORT / TECHNICAL REPORT
FREE ACCESS
A 2/3-inch 760k pixel interline transfer CCD (IT-CCD) image sensor has been developed, which includes twice as many vertical pixel numbers as the conventional 380k pixel CCD image sensor within the same image format, and independent 8 vertical bus lines. These features enable the sensor to be applicable not only to NTSC system (525-line interlace mode), but also to vertical high resolution TV system (525-line progressive mode and 1049-line interlace mode). Furthermore, various application, such as dynamic range expansion mode and smear elimination mode, can be realized for its high driving flexibility.
View full abstract
-
Article type: Appendix
1996 Volume 20 Issue 23 Pages
App1-
Published: March 19, 1996
Released on J-STAGE: October 13, 2017
RESEARCH REPORT / TECHNICAL REPORT
FREE ACCESS