The local corrosion of nickel can occur during the gold plating in AU/Ni fabrication processes. The wire bonding strength decreases as the nickel is diffused to the gold surface by the heat treatment. Accordingly, palladium plating is generally applied as an interlayer between the nickel plating and the gold plating to avoid the local corrosion of nickel. However the influence of the nickel layer structure and the noble metal film thickness on the wire bonding strength has not been investigated in detail. In this study, we investigated how the structure of the deposited nickel and the thickness of the noble metal film influenced the wire bonding properties. The bonding strength of nickel was higher with a layered structure than with a columnar structure when the gold and palladium films were 0.05μm thick.

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Electromigration in the Cu/In/Cu flip chip joint system was investigated at a temperature of 398 K with a current density of 20 kA/cm². Indium was transported towards the anode, and a large void nucleated by electromigration at the In/Cu₁₁In₉ interface in the highest current density region near the cathode. It was found that a unique solder bump deformation towards the cathode occurred in the early stage of the electromigration test, when no underfill material was used. When the underfill material was used to fill the space between the chip and the substrate, the electromigration lifetime in the joint was prolonged by more than ten folds in comparison with that of the joint without underfill. This was a result from that indium transport was inhibited due to a larger backstress induced by the constraint of the underfill.

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We have successfully developed a novel Package-on-Package (PoP) technology for achieving small package thickness and low package warpage. The novel package structure is based on an ultra-thin coreless substrate, called a Multi-Layer Thin Substrate (MLTS) . The MLTS is fabricated by completely removing the Cu base plate after forming a high-density buildup structure on the base plate. In this paper, however, the Cu posts are formed by selective wet etching of the Cu base plate. Since the novel package has built-in Cu posts as external terminals, the overall substrate can be molded for the peripheral area as well as the chip mounting area. This paper also describes how two types of novel wet etching processes have been developed for obtaining narrower pitch and higher aspect ratio. Through the novel wet etching process, we achieve Cu posts of 0.5 mm pitch and high aspect ratio of 6.0, which cannot be realized by wet etching. A prototype package has 361 pads arranged in 5 rows with 0.5 mm pitch, and the thickness is only 0.23 mm.

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Gold bumps are conventionally used for interconnection of TAB (Tape Automated Bonding), COF (Chip on Film), or COG (Chip on Glass) in the driver LSIs of liquid crystal displays for mobile devices. These bumps are generally formed using cyanide-free gold electro-plating, since electrolytes containing cyanide tend to damage organic photoresist. However, a cyanide gold-plating bath for printed writing boards is also sometimes used to make gold bumps. This study investigated the gold sputtering influence on photoresist profiles and bump shapes after gold deposition.

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The high performance of electronic devices, such as personal computers and cellular phones, has led to an increase in the heat generated by their electronic parts. In printed circuit boards (PCBs) with many electronic parts we encounter higher heat radiation than ever before, and at the same time we require higher reliability. At present, high thermal conductivity PCBs with metal and ceramics substrates are used. In this study, we were attracted to anodized aluminum film for its non-conductivity and high thermal conductivity properties. By using the anodized aluminum film as an insulating layer, we succeeded in making a PCB with excellent non-conductivity and high thermal conductivity.

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Remarkable progress has been made in the development of electronic devices, especially in portable applications. This field requires packaging technologies that allow for smaller structures with higher density. To satisfy this demand, a W-CSP (Wafer-level Chip Size Package) with a resin stress buffer layer has been developed. The incredibly small package size and simple structure of the W-CSP creates an important issue: how to decrease thermal mechanical stress caused by differences in the coefficient of thermal expansion between the IC chip and the daughter substrate. In this paper, we describe the development of a W-CSP structure that includes a resin stress buffer layer with high thermal cycle reliability for BLTs (Board Level Tests), using thermal mechanical analysis and a novel W-CSP structure with two redistribution circuit layers. The lifetime of this novel structure is twice as long as that of an ordinary W-CSP for a thermal cycle BLT.

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