ITE Technical Report
Online ISSN : 2424-1970
Print ISSN : 1342-6893
ISSN-L : 1342-6893
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23.57
Displaying 1-17 of 17 articles from this issue
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  • [title in Japanese]
    Article type: Cover
    Pages Cover1-
    Published: September 20, 1999
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.23.57.0_Cover1
    CONFERENCE PROCEEDINGS FREE ACCESS
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  • [title in Japanese]
    Article type: Index
    Pages Toc1-
    Published: September 20, 1999
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.23.57.0_Toc1
    CONFERENCE PROCEEDINGS FREE ACCESS
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  • Chip Level Analysis Method of Substrate Noise
    Yoshitaka Murasaka, Makoto Nagata, Takashi Morie, Atsushi Iwata
    Article type: Article
    Pages 1-8
    Published: September 20, 1999
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.23.57.0_1
    CONFERENCE PROCEEDINGS FREE ACCESS
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    In order to design highly accurate AD mixed-signal LSIs, chip level analysis of the substrate noise is required. We devised the method to make a substrate equivalent circuit model with Fundamental matrix opreration and developed the analysis method of the substrate noise with parasitic effect of chip assemble. The number of nodes of the substrate equivalent circuit can be reduced without the loss of accuracy. These methods enable large transient analyses of the chip level substrate noise with resonable analysis time.
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  • On-chip active guard band filters to suppress substrate-coupling noise in mixed-signal integrated circuits
    Keiko Makie-Fukuda, Toshiro Tsukada
    Article type: Article
    Pages 9-14
    Published: September 20, 1999
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.23.57.0_9
    CONFERENCE PROCEEDINGS FREE ACCESS
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    An AC coupling configuration of active guard band filters can supply a substrate-coupling-noise cancellation signal to a ground-level substrate by using a single 3-V supply to on-chip circuits. Noise was suppressed to a maximum of less than 0.05 from 100 Hz to 2 MHz in a 0.35-μm CMOS test chip. Experiments and a simulation based on the substrate model showed that the noise-suppression effect depends on the guard-band arrangement. The simulation is thus effective for optimizing the arrangement to strongly suppress noise effects.
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  • Measurements and Analyses of Substrate Noise Waveform in Mixed Signal Environment
    Makoto Nagata, Daisuke Tamura, Takashi Morie, Atsushi Iwata
    Article type: Article
    Pages 15-20
    Published: September 20, 1999
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.23.57.0_15
    CONFERENCE PROCEEDINGS FREE ACCESS
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    A transition controllable noise source is developed in 1 0.4μmCMOS, P-substrate N-well technology, for experimental studies on substrate noise properties in a mixed signal IC environment. The number of active logic elements, transition directions, and delays can be controlled. Measured substrate noise waveforms with 100ps time resolution show that peaks in substrate voltage reflecting logic transition frequencies have a time constant a few times large than the switching time. Analyses with equivalent circuits make it clear that this process results from charge transfer between parasitic capacitance of entire logic circuits and an external supply, through suppy/return parasitic impedance.
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  • Area Auto-Focus CMOS Sensor with new Noise Cancellation Circuits
    Hidekazu Takahashi, Mahito Shinohara, Shigetoshi Sugawa
    Article type: Article
    Pages 21-28
    Published: September 20, 1999
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.23.57.0_21
    CONFERENCE PROCEEDINGS FREE ACCESS
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    We have developed a new CMOS area sensor for an auto-focus camera system. This device has been developed for our AF SLR(Auto-Focus-Single-Lens-Reflex) camera EOS-3 that realizes 45-point area AF. The area AF CMOS sensor is fabricated using 1.2μm CMOS process, which consists of new CMOS sensor cells, new CMOS memory cells, signal trasfer cicuits and peak monitor circuits. This device realizes low noise characteristics by new noise cancellation technology. The area AF CMOS sensor exhibits excellent performance such as a high sensitivity and wide dynamic range. In addition, this area AF sensor realizes the low power consumption, high-speed readout and on-chip peripheral circuit.
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  • Design and Process-Development of CMOS Image Sensor Overlaid with a HARP Photoconversion Layer
    T. Hayashida, T. Tajima, S. Yamauchi, M. Kosugi, H. Ootake, Y. Ishigur ...
    Article type: Article
    Pages 29-36
    Published: September 20, 1999
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.23.57.0_29
    CONFERENCE PROCEEDINGS FREE ACCESS
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    We studied CMOS image sensor overlaid with a HARP film. The high edurance voltage MOS transistor and process of connecting HARP film and CMOS image sensor is essential on this research. For the former, MOS transistors, of which endurance voltage is 53V was achieved by using the DDD(Double Doped Drain)structure. Aiming at increasing endurance voltage of DDD-MOS, a new transistor structure was proposed and simulated. For the latter, revealing the problems on the In micro bump process to connect the HARP film and the CMOS image sensor, a polyimide-core bump process was proposed. Finally, the evaluation of the test device is described.
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  • 128×64 pixels adatpive-integration-time image sensor
    Takayuki HAMAMOTO, Yoshikazu INO, Kiyoharu AIZAWA
    Article type: Article
    Pages 37-43
    Published: September 20, 1999
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.23.57.0_37
    CONFERENCE PROCEEDINGS FREE ACCESS
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    We have been investigating the adaptive-integration-time image sensor. In this paper, we describe a new adaptive-integration-time image sensor based on a column parallel architechture which has 128×64 pixels. In this new prototype, the scheme to control integration time is much extended, and pixel pitch, processing speed and power consumption are much improved in comparison with our previous prototype. It has the circuits for detection of saturation and motion. Both integration time and output timing of the pixel value are controlled by any combination of three elements, which are motion detection, saturation detection and external signal. We have fabricated a prototype using CMOS 0.8μm process and show results of some experiments.
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  • A Functional CMOS Image Sensor Using PWM Signals
    N. Takeda, M. Honma, D. Nomasaki, M. Nagata, T. Morie, A. Iwata
    Article type: Article
    Pages 45-52
    Published: September 20, 1999
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.23.57.0_45
    CONFERENCE PROCEEDINGS FREE ACCESS
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    A functional CMOS image sensor utilizing merged analog-digital circuit architecture based on pulse width modulation(PWM)method is proposed. In addition to row-parallel gray scale readout, thresholding, and using a PWM signal addition techniques based on switched current integration and charge paket counting, 2D-projections and block summation were realized. The test chip was implemented with a 0.8μm CMOS technology with 3.3V power supply, and the operations of 2D-projections and block summation were confirmed by experiments.
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  • A Motion Vector Estimation Circuit Using PWM Signals
    Y. Banmoto, M. Nagata, T. Morie, A. Iwata
    Article type: Article
    Pages 53-59
    Published: September 20, 1999
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.23.57.0_53
    CONFERENCE PROCEEDINGS FREE ACCESS
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    A motion vector estimation circuit, necessary for moving picture encoding, is implemented based on the A-D merged circuit architecture using pulse-width modulation(PWM)signals. This circuit contains a PWM memory that stores reference picture data, a distance calculation circuit array, a minimum detecting circuit, a PWM signal shift circuit. The minimum detecting circuit searches the vector with minimum value using a latch comparator. The PWM signal shift circuit enables parallel calculation in search area by shifting PWM signal using a ramp generator and a chopper comparator. We implemented a test chip with 0.6um CMOS technology. This method demonstrate 12.4GOPS processing capability, 380GOPS/W energy efficiency for motion vector estimation at 720pel×480pel, 480frame/s, search area ±2.
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  • High-speed Interpolated CMOS Image Sensor Based On Bidrectional Multiple Charge Transfer and Its Application to Motion Vector Estimation
    Dwi HANDOKO, Shoji KAWAHITO, Yoshiaki TADOKORO, Akira MATSUZAWA
    Article type: Article
    Pages 61-66
    Published: September 20, 1999
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.23.57.0_61
    CONFERENCE PROCEEDINGS FREE ACCESS
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    A huge computational complexity of motion vector (MV) estimation is the main contributor to the large power moving picture encoders. For high definition image, it is difficult to implement a onechip MV estimator. This paper proposes a CMOS image sensor with high-speed interpolated image sensing and an iterative block matching methods to estimate MV using the interpolated pictures. The proposed method reduces the computational complexity greatly. In order to improve the image quality of the high-speed interpolated pictures, this paper also proposes a new technique for interpolated image sensing, so called a bidirectional multiple charge transfer. Analysis results of the proposed sensor are also shown.
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  • Development of a CMOS Imager with Motion Detectors
    Y. Fujimoto, F. Okamoto, T. Nagata, M. Furumiya, K. Hatano, Y. Nakashi ...
    Article type: Article
    Pages 67-74
    Published: September 20, 1999
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.23.57.0_67
    CONFERENCE PROCEEDINGS FREE ACCESS
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    A new CMOS imager with motion detectors has been developed. This chip can detect motion of the projected objects and scan the window-shaped area in which motion is detected, which improves the frame speed and effectively reduces the data amount to be transferred to the successive boards. Sparsely placed motion detectors in the sensor array detect motion regardless of frame speed with little reduction of pixel density. Other important circuits in developing this chip include a unity-gain pixel amplifir and multi-stage column readout circuits. A 5.8mm×8.7mm chip fabricated by using 0.35μm CMOS process contains 192×192 pixels and 7×7 motion detectors. Experimental results have successfully confirmed the functions of the motion detectors and the local scan.
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  • A CMOS Image Sensor with Logarithmic Compression Response and its Application
    Masaaki SASAKI, Shoji KAWAHITO, Yoshiaki TADOKORO
    Article type: Article
    Pages 75-82
    Published: September 20, 1999
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.23.57.0_75
    CONFERENCE PROCEEDINGS FREE ACCESS
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    A active pixel sensor with logarithmic compression response is sattracted as a wide dynamic range image sensor. This paper presents a method for setting arbitrary nonlinear photo conversion charanteristic based on a fact that the level shifting in logarithmically compressed domain is equivalent to the gain in the exponentially expanded domain. The logarithmic conversion is performed in each pixel using subthreshold region of MOSFET. The exponentially expansion using a substrate bipolar transistor is performed at the output of the CMOS image sensor chip. As another important topic of the CMOS image sensor with logarithmic compression response is to cancel the fixed pattern noise(FPN). This paper also presents a method to cancel the FPN using only 4 transistors in each pixel.
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  • A CMOS Integrated 2-D Fluxgate Magnetic Sensor
    Shoji Kawahito, Christoph Maier, Michael Schneider, Henry Baltes
    Article type: Article
    Pages 83-89
    Published: September 20, 1999
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.23.57.0_83
    CONFERENCE PROCEEDINGS FREE ACCESS
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    This paper presents an integrated 2D micro fluxgate magnetic sensor based on standard CMOS technology and simple post processing for magnetic film preparation. The system contains, on a monolithic chip, two orthogonal planar microfluxgate sensors and the complete electronics for fluxgate excitation and signal readout. The system uses on-chip A/D conversion with digital feedback in magnetic flux. The angular resolution to 50 uT 2D vector magnetic induction is about 4 degree. The applications comprise geomagnetic navigation, non-destructive material testing, 2-D/3-D magnetic mouse, and micro magnetic heads as scientific measurement tools.
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  • CMOS Image Sensor Technologies
    Yoshiyuki Matsunaga
    Article type: Article
    Pages 91-98
    Published: September 20, 1999
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.23.57.0_91
    CONFERENCE PROCEEDINGS FREE ACCESS
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    Recently, CMOS type image sensors are increasingly required as image pick-up devices. Here, their constructions, on-chip A/D converters, analog parts and fabrication technologies are described. In near future, high performance one-chip-cameras will be realized with new low noise technologies on them.
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  • Status and Future of Silicon Sensors and MEMS
    Masayoshi ESASHI
    Article type: Article
    Pages 99-106
    Published: September 20, 1999
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.23.57.0_99
    CONFERENCE PROCEEDINGS FREE ACCESS
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    Advanced silicon sensors and MEMS(Micro Electro Mechanical Systems)have been realized based on silicon micromachining. Active catheters which move like a snake using distributed microatuators and ultrasonic imager used for the catheter have been developed. Deep RIE and XeF_2 silicon etching have been applied for precise micromachining. Electrostatically levitating micro motor was developed for the purpose of high performance gyroscope. By applying this technology ceramic micro-structures were fabricated using micromachined silicon as a mold. Capacitive AFM/SNOM probe, nanomachining to fabricate very small stylus and near field lithography to transfer nano-scale pattern have been developed.
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  • [title in Japanese]
    Article type: Appendix
    Pages App1-
    Published: September 20, 1999
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.23.57.0_App1
    CONFERENCE PROCEEDINGS FREE ACCESS
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