We propose a Single-Slope ADC with a time to digital converter(TDC) that uses a quadrature-phase-detection instead of a multi-phase clock. The TDC that uses a multi-phase clock is often used in previous studies. We designed and fabricated a 12-bit ADC which consists of the 3-bit TDC and the 9-bit Single-Slope ADC, by using a 0.18-μm CMOS process. Specifically, it consists of an amp, latched comparators, an encoder, a 9-bit counter, and a data buffer for Correlated Double Sampling(CDS). In a previous study, 3-bit TDC has 4 stages. However, in this study, the TDC has 2 stages. We also confirmed time variation reduction of shoot-through current by Spectre simulation.
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