Asymmetric parallel-coupled coplanar waveguide (CPW) is originally characterized here as an equivalent unified K-inverter network. On a basis of our developed self-calibrated method of moments (MoM), the relevant network parameters are extracted to explicitly demonstrate the frequency-dependent coupling behavior with the 1^st zero coupling at the λ/2 length of overlapped section. By differentiating the coupled spaces and overlapped lengths, the two CPW coupling structures are dissimilarly constructed and utilized as the input/output excitation of a λ/4 CPW bandpass filter. Through allocating the two unequal zeros towards the spurious harmonic around 3λ/4, an improved two-stage λ/4 CPW filter is designed at 5.0GHz. Optimized results achieve broad rejection band, ranging from 5.8GHz beyond 18.0GHz, as verified by the ADS simulation.

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The circularly polarized post-wall waveguide array is designed and fabricated for the first time. The aperture illumination and the characteristics of the antenna are investigated by using analysis/design method developed for oversized rectangular waveguide slot arrays. The uniformity as well as the polarization is perturbed along the periphery of the aperture; the narrow walls are identified to be the dominant factors for degrading the amplitude uniformity and the polarization purity in the aperture illumination. The peak gain of 29.3dBi with 39.7% efficiency is realized at 77GHz band for the antenna with about 5cm square aperture.

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In this paper, we propose the efficient flexible hybrid arithmetic unit for elliptic curve cryptographic applications which executes addition, multiplication and inversion in GF (2^m). The proposed flexible hybrid GFAU is beneficial in cost-effectively implementing microprocessors' elliptic curve public-key extensions. It targets applications for smart cards whose gate count is below 20,000.

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To improve analog design automation (ADA) of electronic circuits, an interactive system for symbolic analysis called SIASCA is introduced. SIASCA includes schematic capture of a more general class of analog circuits, namely: operational transconductance amplifiers and current conveyors. The options of analysis are focused on calculating simplified symbolic expressions (SEs), representing the dominant behavior of a circuit, for AC and noise analysis. To minimize complexity in manipulating SEs, all active devices are modeled at different levels of abstraction by using nullors. Several examples demonstrate the suitability and usefulness of SIASCA to be used within ADA environments.

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