This paper presents a generic analytical performance model of Network-on-Chip (NoC) router, which is further used to analyze the performance of a whole wormhole NoC. We focus on the analysis of various packet blocking-conditions at the router input-queues for a more accurate estimation of waiting time. Based on this estimation, some key performance metrics of NoC, such as the buffer utilization and packet transfer latency, are both computed. Compared with some previous model, it presents more accurate results: for buffer utilization ratio, the error is 6.30%; for packet transfer latency, it is about 5.98%.

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In order to reflect a realistic wireless channel as closely as possible, the channel model becomes very complicated and is thus prone to error when implemented as a channel simulator. However, there is no rigorous way of verifying the implementation of the channel simulator. We propose a novel verification methodology that aims at implementing a verified channel simulator for the IMT-Advanced channel model. We first derive a systematic description of the channel model, where a random waveform is generated through various deterministic functional blocks and independent random number generators. We then verify the deterministic functional blocks by adopting the vector-based software verification methodology.

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This paper propose an area-efficient pipeline-balancing Reed-Solomon decoder for 10Gbps satellite communication. The proposed RS (244,212) is based on TD-iBM Key Equation Solver architecture, and Fixed-Factor Syndrome Computation & Chien Search. The decoder is implemented and verified in FPGA, and can work at 178MHz in Virtex2P. Thus a 8-channel FPGA implementation can be used for 10Gbps satellite communication systems. Additionally, the decoder is also synthesized in Chartered 90nm CMOS technology, and compared with previous decoders. The results show the decoder is more area-efficient than previous decoders. Meanwhile, by using this CMOS technology, the decoder can be clocked at about 1350MHz, so a single-channel ASIC implementation can meet the requirement of 10Gbps satellite communication.

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In this paper, we propose a structure for independent null steering by decoupling complex weights. It has the advantage of independent steering of(N-1) nulls for a linear array having N elements and the complex weights are decoupled such that each weight corresponds to a particular null. For this purpose, the position of each zero of the array factor on the unit circle in the complex plane is controlled by the corresponding weight in the structure. It means that if a single jammer changes its position, only a single corresponding complex weight has to be recalculated, which reduces computational complexity.

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This paper presents a new Post Distortion Cancellation (PDC) Gilbert-mixer for Ku-band applications to minimize the third-order nonlinear current of transconductance transistors. To illustrate the effectiveness of this scheme, distortion analysis using Volterra series is given. An extra inductor is added between source nodes of switching transistors to decrease the deteriorating effect of parasitic capacitances. The proposed mixer has been simulated in a 0.18-µm RF-CMOS technology and consumes only 6-mW from a 1.8-V supply. Compared to conventional Gilbert-mixer, it typically improves IIP3 by 4.2dB, power conversion gain by 1.1dB and noise figure by 1.4dB.

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This paper introduces a displacement mapping algorithm that represents protruded shapes on the surface of an object. Two verticalsurfaces that are perpendicular to the underlying surface are added along the boundary of the polygon surface in order to represent pixels overflowing acrossthe boundary of the polygon surface. The proposed approach can accurately represent the silhouettes of protruded shapes. Using per-pixel instructions on graphics hardware, the approach is accelerated and executed in real-time. The proposed method provides an effective solution for the representation of protruding shapes such as high-rise buildings in an urban environment which can be used in location based applications of mobile electronic devices.

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In this paper a novel spiral compact microstrip resonant cell (NSCMRC) to design a low pass filter with wide stopband is presented. The slow-wave effect and scattering and radiation parameters are depicted. The designed lowpass filter is implemented by cascading three cells with different dimensions that shows the advantages of low insertion loss less than 0.03dB and wide stopband from 4GHZ up to 50GHZ with suppression level better than -13.4dB and compact size. Finally, the proposed lowpass filter is fabricated and a good agreement between simulated and the measured results are demonstrated.

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A CMOS 80-400MHz fifth order Chebyshev Gm-C low pass filter with a unique auto tuning system is presented. Both Gm and C are tuned digitally leading to a 5X tuning range. A digital magnitude-locked loop liked tuning system is proposed. The tuning system uses a digital calibration scheme, broadening the tuning range dramatically. A fifth order Chebyshev Gm-C filter with the proposed auto tuning system was designed with TSMC 0.13µm RF CMOS process for verification. Measurement results show that the cut-off frequency of the filter can be tuned between 80-400MHz, with an average tuning error of no larger than 3.6%. The dynamic range of the filter for THD less than 1% is 60dB. The power dissipation is only 5.5mW with 1.2V supply voltage.

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Mixed Radix Conversion is an essential feature of error detection and correction in Redundant Residue Number Systems. Fermat numbers are a popular choice as moduli in these systems. However, Fermat numbers are typically implemented using Diminished-1 arithmetic which necessitates special consideration of zero in arithmetic operations. Furthermore, the sequential nature of Mixed Radix Conversion leaves it prone to considerable delay due to carry propagation in adders at each stage. In this paper, Diminished-1 arithmetic in carry save form is used to give significant reductions in area and delay compared to previously proposed hardware architectures. The percentage area reduction was found to range from 13% to 41% and that of delay from 19% to 49% for bit widths from 8 to 28bits.

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The main section of this paper has mentioned to design considerations for conductive enclosure. Firstly, shielding effectiveness is investigated for various shielded enclosures. Also, amount of increase in shielding effectiveness is obtained by double layer shields. Next, the influence of apertures and its equivalent rectangular slot are explained. Shielding effectiveness is analyzed for shielded enclosure with waveguide slot, empty shielded enclosure and shielded enclosure with substrate, separately.

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A CMOS voltage controlled oscillator (VCO) topology is proposed to suppress the flicker noise up-conversion, thus improving its close-in phase noise performance. The idea is based on a previous work relying on insertion of resistors in series with the conducting channel resistors of the complementary cross coupled pairs. The immunity of the loaded quality factor (Q) to the conducting channel resistors which are modulated by their flicker noise is enhanced, thus reducing the flicker noise up-conversion gain. In the proposed topology, the VCO oscillation amplitude is not degraded and the resistance is never constrained by the threshold voltage, which are problems of the previous topology. Meanwhile the number of resistors is halved, lowering circuit complexity. Two VCOs based on the previous topology and the proposed topology are designed in a 65nm CMOS process. Simulation results show the phase noise of the proposed VCO is improved by more than 4dB at 1kHz offset frequency and 2dB at 10kHz offset frequency over the whole 2.85GHz to 3.75GHz tuning range.

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We propose effective texture-mapping hardware for real-time ray tracing. Therefore, we introduce a novel method to select the MIP-map level of texture images, which requires only the total length of the intersected ray and the pre-calculated value. The proposed architecture can support the texture MIP-mapping by integrating simple hardware logic in existing ray-tracing hardware.

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At 60GHz, it becomes difficult to achieve a high power added efficiency (PAE) and large output power for CMOS power amplifier (PA). A parallel class-A and AB pseudo Doherty PA is designed in CMOS 65nm process to obtain a high PAE and large output power. The PA achieves a 9.8-dB gain at 60GHz. The measured large signal results show that a maximum power added efficiency (PAE) of 14.3% and 12.0% at 1dB compression point are realized. The chip consumes 45∼58mW power from a 1.2-V supply voltage. The chip area is 0.6mm² including pads.

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In this paper a novel method to increase the modulation bandwidth of vertical-cavity surface-emitting lasers (VCSEL) is proposed. The modeling predicts that the modulation bandwidth can be enhanced by 60% with lateral optical feedback. Even if the relaxation oscillation frequency is below 15GHz without optical feedback, the modulation bandwidth can reach at 40GHz beyond the limit of a relaxation oscillation frequency. Small and large-signal-modulation analysis is carried out. The result shows a potential of high-speed modulation beyond 40Gbps for use in low-power consumption optical interconnects.

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Background modeling is important in video surveillance for extracting foreground regions from a complex environment. In this paper, we present a novel background modeling technique based on a special type of Markov Chain. The method is a substantial extension to the existing background subtraction techniques. First, a background pixel is statistically modeled by a linear regressive Gamma Markov distribution. Then, these statistical estimates are used as important parameters in background update schemes. The experimental results show that the proposed model is less sensitive to movements of the texture background and more robust for real time segmenting the foreground object accurately.

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This letter takes a new approach to extract a closed-form expression for the bit error rate (BER) of direct-sequence ultra wideband (DS-UWB) system. In the analysis, the main signal is impaired by multi-user interference (MUI) and an external source of interference originated by simultanously transmitting multiband orthogonal frequency division multiplexing (MB-OFDM) systems which are located in the vicinity of the DS-UWB receiver. All the transmission channels are affected by Nakagami-m fading. A Laplacian distribution is considered for MUI to comply more with real statistical behaviors of this kind of interference.

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In the present work, a new structure of vertical cavity surface emitting laser (VCSEL) is designed and simulated. In this structure, InGaAsP is used as the active region which is sandwiched between GaAs/AlGaAs distributed bragg mirror at the top of structure and GaAs/AlAs distributed bragg mirror at the bottom. In this work, the hole etching depth was continued down to the top of lower spacer layer while in the previous work the hole etching depth was only down to top of the upper spacer. In this way, the threshold current decrement of 76.52% and increment the power by 28% from 5mW to 6.4mW at bias current of 9mA was achieved. In this paper, device characteristics such as light power versus electrical current and voltage versus current are simulated and compared with the previous work.

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Network-on-Chip (NoC) is proposed as a scalable and reusable communication platform for future embedded systems. The performance of NoC largely depends on the underlying deadlock-free and efficient routing algorithm. In this paper a novel fully adaptive routing algorithm for avoiding congested areas using a fuzzy-based routing decision is proposed. The objective of the proposed routing algorithm is to choose a channel that has more free-slots input buffer and lower power consumption. The routing path is established by minimizing a cost which is calculated by a fuzzy controller which considers the power consumption and free slots input buffer of cores. The performances evaluation is carried out by using a flit-accurate simulator under different traffic scenarios. Experiment results show that the routing algorithm can effectively improves the average delay and power distribution to meet the power balance requirement and avoid hotspots with low hardware overhead.

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