In this paper, a new method for designing dual band microstrip antenna is presented. This method can be used to design any dual band microstrip patch antenna with arbitrary resonant frequencies and different frequency ratios. In this method, non-regular polygonal patch is used to design dual band microstrip antenna and particle swarm optimization (PSO) technique and ant colony optimization (ACO) are used to optimize the shape of the patch antenna. This method is used to design a dual band microstrip antenna for satellite application, which has resonant frequencies at 8.6 and 13GHz.

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We demonstrate a Colorless, Directionless, and Contentionless add/drop that is made possible by newly proposed multi-stage tunable filters; it will be effective in the creation of flexible and dynamic optical path networks. The filters consist of small-scale switches and AWGs (Arrayed Waveguide Gratings) and so are cost effective. The technical feasibility of the drop configuration using proposed tunable filters is experimentally verified.

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A compact monopole ultra-wideband (UWB) antenna with WiMAX band rejection is proposed. The proposed antenna is optimized to be 12×18mm² in size and cover the frequency band from 3.1 to 11GHz with rejection of the WiMAX band. The antenna is simulated, fabricated, and tested; the measured results show good agreement with the simulation results. The proposed antenna presents satisfactory radiation characteristics.

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In this paper, we propose a critical-path based timing driven FastPlace, named TimFastPlace, which uses an iterative critical path-based weighting model to optimize the critical path delay at the equation solving stage. Experimental results on several industry cases and ISCAS89 cases show that we are able to obtain up to 30.83% Worst Negative Slack (WNS), an average of 23.42% WNS and 18.87% Total Negative Slack (TNS) improvement in circuit delays at an average of 2.54% wire length increase. Besides, runtime is kept at the same level as FastPlace.

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Antenna polarization states always vary with scan direction which can be named as Spatial Polarization Characteristic (SPC) of antenna. We present a novel antenna module named orthogonal polarization binary array antenna (OPBAA). The advantage of the design is its simple design and prominent SPC. Which can be used for polarimetric application. The theoretical model is derived and spatial polarization characteristic is especially analyzed. Measurement results of an OPBAA formed by two horns are analyzed to verify the conclusions. The OPBAA can reduce the complexity of the communication system which has good application prospect in the future.

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A high voltage half bridge gate driver with mismatch-insensitive dead-time generator is proposed. The high voltage high-side level shifter with common-mode noise canceller technique guarantees the stable operation in negative output voltage level. Unlike a conventional dead-time generator, the proposed dead-time generator uses one delay cell to generate dead-time and shares it with the high-side and low-side paths. The high-side gate driver allows stable negative operation up to -10.2V DC level and -40.5V peak level at 15V power supply. Measurement results of proposed dead-time generator show 1.7 times and 16.7 times improvement of dead-time mismatch when dead-time is 350nsec which is minimum set value and 5µsec, respectively, compared to the conventional dead-time generator.

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We investigated nitrogen-rich HfN insulator on p-Si(100) substrate to prevent to form an interface layer with low dielectric constant by electron-cyclotron-resonance plasma sputtering method for the first time. The nitrogen concentration in the deposited HfN film was confirmed as approximately Hf:N = 1:1.2. Furthermore, the electrical properties of Al/HfN/p-Si(100) gate stack were improved by hydrogen anneal compared to nitrogen (N₂) anneal. The EOT of 0.64nm with low leakage current of 6.2×10^-4 A/cm² (@ V_FB -1V) was obtained. The results suggest that the effect of hydrogen anneal attributed to improve the electrical properties of HfN gate dielectric.

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This paper is about the implementation of a novel booth encoder-decoder in a 0.35µm CMOS technology. By introducing a new truth table, the gate level delay from inputs to partial products is reduced to two XOR logic gates plus one transistor which is the main advantage of the proposed architecture. Also, the gate count is reduced which reduces the power dissipation. In addition, because of similar paths from inputs to outputs, the latency for all paths becomes equal. Therefore, the output waveforms will be free of glitch. Post layout simulations demonstrate that the delay of the whole system is 350ps.

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A compact dual-band bandpass filter using loop resonators is proposed in this paper. The filter is designed for resonance frequencies of 1.8GHz and 2.4GHz. It is fabricated on RT/Duroid 6010 with h = 1.27mm and a relative dielectric constant ε_γ = 10.8. This filter has achieved excellent scattering parameters and size reduction of approximately 30% compared to conventional microstrip filters. The measured fractional bandwidths are 1.66% and 3.54% at 1.8GHz and 2.4GHz, respectively. The filter is evaluated by simulation and measurement with very good agreement.

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A novel substrate integrated waveguide (SIW) filter with source-load coupling based on low temperature co-fired ceramic (LTCC) technology is proposed. By introducing mixed coupling into input/output SIW in middle layer, the filter not only has good selectivity owing to the controllable transmission zeros, but also has a compact size by the virtue of LTCC structure. Based on the flexible coupling manner in multilayer structure, a demonstration second-order bandpass filter with three transmission zeros has been designed and fabricated. Good agreement between measured and simulated results is observed.

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This paper details the design of a 64×32bit 4-read 2-write register file in TSMC 65nm LP process. The register file avoids cell banking with pseudo-differential sensing scheme. Moreover, this approach enables a fully shareable and completely symmetry cell layout which shows competitive area results. Non-full-swing technique is proposed to avoid over design and improve energy efficiency. As for the timing control module, clocked pull-down circuit cuts off a possible short-current path at high clock frequency. A prototype is implemented in TSMC 65nm LP technology. The measured results demonstrate operation of 0.77GHz, consuming 7.08mW at 1.2V, and occupying 0.018mm².

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This paper presents a design of buck-current-fed full-bridge zero current switching converters which are suitable for high-power high-voltage DC applications. This study shows the capability of incorporating the step-up transformer parasitic components to get the zero current turn-off characteristics for full-bridge switches. The buck stage of the converter uses pulse-width-modulation control to regulate the output voltage and the full-bridge stage operates at a constant on time mode to implement soft-switching commutations. In this study, the converter model is derived, and this model is implemented in an IsSpice circuit, which can reveal the transient characteristics of the converter. Steady state analysis of the converter is also presented. Finally, the simulation results of this converter for the application of coupled cavity traveling wave tube are given and major design issues are discussed.

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