Composite insulation equipment is widely used in power systems, and the detection of internal material interface defects is an important and difficult task in power grids. Terahertz wave can help detect internal faults in equipment in a timely manner, but the analysis of large amounts of data has brought about significant labor costs. In order to improve the efficiency of Terahertz wave detection, this paper proposes a Terahertz wave defect detection method based on spectrum feature fusion and spiking neural network. By performing multiple wavelet basis transformations on terahertz wave timing waveforms, and then performing feature fusion extraction on the data through a self encoder incorporating spatial and channel attention mechanisms, the differences between different defect detection waveforms are expanded. Then, spiking neural networks are used to classify the feature fused spectra to obtain defect detection results. Compared with other typical models, this model performs better in terms of accuracy and training costs.

Blade-type phase-change random access memory (PCRAM) has recently become one promising candidate to compete with conventional PCRAM devices for next generation on-chip storage. This can be ascribed to its sharp contact region at heater-phase change layer interface, significantly lowering resulting energy consumption. However, a comprehensive review concerning the physical principles, current status, and possible improvements of blade-type PCRAM is still missing. To address this issue, here we first reviewed common phase-change materials for storage applications and physical principles of blade-type PCRAM. Subsequently, the current status of blade-type PCRAM from both experimental and theoretical perspectives was described as well as the performances comparison with conventional PCRAM. Possible approaches to overcome the technical challenges of blade-type PCRAM and its future prospect were eventually discussed.

This paper presents a 45w (20V, 2.25A) output active clamped flyback (ACF) AC-DC controller using a capacitor-coupled integrated digital isolator in isolated communication in place of a bulky optocoupler, which not only helps to reduce system volume but also improves the reliability of the ACF converter. In contrast with the conventional ACF, the controller in this paper features a delicate adaptive zero voltage switching (ZVS) control to reduce conduction and switching losses so as to improve the power efficiency. Designed in a 0.18-µm isolated BCD process, the simulation result shows the proposed ACF converter approached 95.1% maximum efficiency when GaN power transistors are used as power switches. The feasibility of the proposed digital isolator is also verified and exhibits high transmission accuracy with low propagation delay.

In this paper, a half-bridge gate driver with adaptive output current for GaN HEMTs is introduced. The output drive current of the driver is adapted to the load of GaN HEMTs, by adjusting the W/L size of drive transistors. The rise time of driver is achieved to be basically constant by the adaptive output current adjustment for different load, so noise can be effectively immunized and working efficiency is improved. Based on the proposed adaptive output current drive circuit, a half-bridge gate driver is designed and implemented in the 180nm BCD process. Tested results show the driver has a constant rise time of about 5ns under 5MHz with C_L of 0.5nF, 2.0nF, and 3.5nF respectively.

A fully-integrated inductance-capacitance (LC) voltage-controlled oscillator (VCO) with a wide tuning range and low phase noise was designed and demonstrated in 130nm CMOS technology process. To achieve a higher quality factor (Q) value, a proposed switched capacitor array (SCA) combining 4-bit switched capacitors with large capacitance and 3-bit switched capacitors with small capacitance is adopted, which occupies a small area at the same time. In addition, a varactor array and a tail resistor array are used to provide flexibly dynamic VCO gain adjustment and power consumption adjustment, separately. The measurement shows a continuous tuning range of 48% from 1.9 to 3.1GHz and consumes 9.6mW of DC power from a 1.2V supply voltage (excluding buffers). Furthermore, this design displays the phase noise of 125.63dBc/Hz at 1MHz offset from its 2.5GHz oscillation frequency. The proposed VCO’s measured figure-of-merit including the tuning range (FoM_T) is -197.39dBc/Hz at a carrier frequency of 2.5GHz, which demonstrates the potential of the proposed VCO for application in integrated circuits.

The peak power of the digital predistortion (DPD) will be uncontrollably expand when the power amplifier (PA) is driven in the oversaturated state. To solve this problem, this letter proposes a peak limited digital predistortion method. By filtering the data used for predistortion coefficient extraction, the peak power of the predistorted signal can be effectively controlled. The memory effect of PA is considered during the data filtering. Less data samples are needed for coefficient extraction, which reduces the computational cost. Simulation verifies the effectiveness of the proposed method, and experimental results show that the adjacent channel leakage ratio (ACLR) can have 12.4dB improvement when the tested PA is operated in an oversaturated state.

This paper proposes a 32-bit RISC-V microprocessor for the IoT, which consists of the Hummingbird e203 and a configurable precision COordinate Rotation Digital Computer (CORDIC) coprocessor. Coprocessor is used to enhance the processing power of the system. Custom instructions are added to the original RISC-V instruction set to accelerate complex calculations. Experimental results demonstrate that the coprocessor can process applications 8-9 times faster than software-based approaches and requires fewer instructions. The microprocessor has been synthesized using a FinFET process, achieving a maximum frequency of 952MHZ. It occupies an area of 14,640.5um² and has peak power consumption of 13.5996mW. Compared to previous accelerators, it offers numerous performance advantages.

Carbon nanotube field-effect transistors (CNFETs) are considered the most promising candidate to replace silicon-based devices. In this study, a Strong-ARM dynamic comparator designed with complementary CNFETs was simulated. The circuit delay and energy efficiency were obtained under conditions of small and large signal inputs. Compared with the silicon-based circuit, the speed of the CNFET-based comparator improved by up to 81.6% for the same technology node, whereas the energy-delay product improved by more than one order of magnitude. This study demonstrated the great potential of CNFETs for comparator applications, which can help achieve high-performance analog-to-digital converters or memory readout circuits.

The traditional fixed slope compensation can solve the problem of sub-harmonic oscillation phenomenon in the current-mode controlled single-inductor dual-output (SIDO) switching converter, however, the stability operation range is limited. To overcome this problem, this paper proposed an adaptive slope compensation technology. Taking SIDO boost converter operating in continuous conduction mode (CCM) as an example, the operation principle and control sequence with adaptive slope compensation are analyzed in detail. Based on this, a five-dimensional discrete iterative mapping model is established, and the bifurcation characteristics of the converter under different operating conditions are presented. The research results show that compared with traditional fixed slope compensation technology, the proposed adaptive slope compensation technology can expand the stability range. Finally, the theoretical analysis is verified by simulation and experiment results.