Due to the stacking dies and unequal cooling effiency of different layers, 3D NoC-based systems suffer sever thermal issues. Adaptive routing can alleviate the thermal issues, but current routing algorithms either suffer from the thermal balance or traffic congestion. This paper proposed a collaborative thermal- and traffic-aware adaptive routing (CTTAR) scheme, which considers the traffic and temperature information together and avoids the packets transferring to congested region. Experiments show that, there is 19.4% to 48.4% system performance improvement compared with other routing algorithms under the same thermal limit.
The proposed broadband fully differential single-pole double-throw (SPDT) switch for Ka-band radar with high 1-dB power compression point (P-1dB) and isolation is demonstrated using 0.13 µm SiGe BiCMOS technology. In contrast to traditional circuit, SPDT switch utilizes fully differential topology with virtual grounding, so it also offers cancellation to common mode disturbance. As a result, this SPDT switch will help in improving radar range due to its high P-1dB, high range-resolution and accuracy due to its broad-bandwidth. Further, this paper also introduces the use of asymmetrical tapered inductor in SPDT switch to improve layout area of SPDT switch with normal spiral inductor. Measurement results of fabricated differential SPDT switch with conventional layout has demonstrated a minimum insertion loss of 2.9 dB and an isolation of -39 dB in 25 GHz to 40 GHz frequency-band, and input P-1dB of 12.6 dBm at 34 GHz with 0.47 mm2 area. EM simulation results of compact differential SPDT switch with symmetrically tapered inductor in layout has demonstrated minimum insertion loss of 1.8 dB and isolation of -39 dB in same frequency-band, input P-1dB of 14.1 dBm at 34 GHz with 0.11 mm2 area.
With the continuous development and commercialization of 4G and 5G technology, the bandwidth demand of front-haul IQ data in CPRI/eCPRI increases rapidly, so data in CPRI/eCPRI links need to be compressed. To solve this problem, this paper built a compression/decompression ASIP (Application Specific Instruction-set Processor) module as a subsystem of our front-haul processor system which could choose algorithms flexibly and data compression ratio with low delay and low distortion. Its advantage is that the three compression algorithms are integrated together, and the compression precision is improved through the study of distortion minimization. Through the performance evaluation, the data transmission rate can reach 537.6 Gbps, and the hardware overhead and EVM value are both satisfied.
A charge pump (CP) is widely used in modern phase-locked loop (PLL) implementations. The CP current mismatch is a dominant source of static phase offset and reference spur in the PLL output signals. In this paper, a novel CP with small current mismatch characteristic over a wide output voltage range is proposed. The specially designed dual compensation circuits use the unity-gain feedback operational amplifier and current mirrors to reduce the current mismatch when the output voltage is closed to the supply voltage (VDD) or ground (GND). And the additional feedback transistors are used to reduce the impact from the channel length modulation effect. Post-layout simulation results demonstrate that the output current of the proposed CP in a 40nm CMOS technology is 115µA. Moreover, the current mismatch is less than 0.97µA or 0.84% over the output voltage range from 0.04 to 1.07V covering more than 93.6% of the 1.1V supply. Thus, the proposed CP maximizes the dynamic range, and reduces the phase offset and reference spur of CP-PLLs.
To address the communication needs of high-speed trains such as bullet trains, which require high-speed millimeter-wave wireless links, we developed a high-stability radio-over-fiber system to transmit IEEE802.11ad packets using optical single-sideband (SSB) modulation. The system comprises an optical SSB modulator with automatic bias control and a low-distortion millimeter-wave amplifier stage and is capable of generating and transmitting IEEE802.11ad packets with 16-QAM modulation under an error vector magnitude of 5.8% at frequency of 97.57 GHz over a 45.5-km-long single-mode fiber.
A wideband receiver is designed to detect signals over a broad bandwidth. To increase the receiver’s capability of detecting multiple signals, it is a common practice to apply a window to reduce spectral leakage. The modified periodogram applies a window before auto-correlation and Blackman-Tucky method applies the window after auto-correlation. To the best of authors’ knowledge, no one has compared the performance difference in the context of wideband receiver applications. This study finds that the modified periodogram can better enable a receiver to detect multiple signals with a significant power difference at the expense of reduced frequency resolution and sensitivity.
As a physically secured wireless communication method, a novel configuration which deduces ANDed data decoded from heterodyne detection between two wireless data streams was proposed. As a feasibility experiment, the demonstration of a heterodyne AND operation was conducted by devising an optical system to emulate our novel wireless system. Experimental results testified the principle of our proposed physical layer security.
Due to the high parallelism, Data flow architecture is a common solution for deep neural network (DNN) acceleration, however, existing DNN accelerate solutions exhibit limited flexibility to diverse network models. This paper presents a novel reconfigurable architecture as DNN accelerate solution, which consists of circuit blocks all can be reconfigured to adapt to different networks, and maintain high throughput. The proposed architecture shows good transferability to diverse DNN models due to its reconfigurable processing element (PE) array, which can be adjusted to deal with various filter sizes of networks. In the meanwhile, according to proposed data reuse technique based on parameter proportion property of different layers in DNN, a reconfigurable on-chip buffer mechanism is raised. Moreover, the accelerator enhances its performance by exploiting the sparsity property of input feature map. Compared to other state-of-the-art solutions based on FPGA, our architecture achieves high performance, and presents good flexibility in the meantime.