A new high-frequency power supply rejection (PSR) improvement technique is presented for a low-dropout (LDO) regulator. The proposed technique utilizes a negative capacitance at the gate of the power transistor to enhance the PSR at high frequencies by neutralizing the effect of parasitic capacitances. The simulation results show that the LDO is able to achieve a PSR of −67.9 dB at 10 MHz.
Statistical static timing analysis (SSTA) is one of the most commonly used methods for analyzing timing behavior under process variations (PVs). Monte Carlo (MC) simulation is a straightforward and effective method for SSTA. In this paper, a new sampling method is proposed to improve an MC-based approach by reducing the number of simulation samples. This method utilizes stratification with an importance analysis for the selection of samples of PVs. Extensive simulations are performed to show that the proposed method achieves a better precision on ISCAS 89 benchmarks compared to other MC simulation approaches.
Mission-critical MCU-based systems under severe electrical situations cause malfunctioning by the disturbance in the clock path. MCU-based systems in clockless status loses their contrability in high-current output or glitch-clock injection may destroy status value of flip-flops. In this paper, we propose the automatic clock failure detection and protection by implementing a fully synthesizable edge detector, noise canceller logic and glitch-free clock changer circuit. To determine several noise-vulnerable data/clock paths, we propose a pre-simulation framework to reconstruct a clock noise propagation path from the entire circuit netlist. We successfully increased the noise immunity characteristics by allocating the detector units into efficient locations.
This paper uses the transmission line to implement the inductive feedback cascode amplifier to achieve 16.9% group delay variation from 22 GHz to 27 GHz. The transfer function of the second-order all-pass network, derived from the two-port Y-parameter, is applied to synthesize the group delay. A prototype, fabricated in the 0.13 µm CMOS technology, is characterized through the on-wafer testing. The measurements show a power consumption of 12 mW from 1.2 V, an amplifier gain of 11 ± 0.4 dB, a noise figure (NF) of 5.1 ± 0.4 dB and a group delay of 71 picoseconds (ps) with a variation of ±6 ps from 22 GHz to 27 GHz. From 21 GHz to 27 GHz, the measured input 1-dB compression point (IP1dB) and the input third-order intercept point (IIP3) are higher than −9.2 dBm and +4.2 dBm, respectively.
This paper presents a fully-integrated and compact multi-band and multi-mode power amplifier for commercial quad-band GSM, dual-band TD-SCDMA and mono-band LTE cellular terminals. To reach a compromise among the performance in terms of efficiency, harmonic suppression and miniaturization, a Class-E PA and a linear PA cores are employed with harmonic-trap immersed output matching networks for low and high band, respectively. Experimental results suggest that the PA generated an output power higher than 33 and 30.5 dBm for low and high band, respectively, with considerable PAE across the operating bands when applied CW signals, as well as favorable ACPR performance for GMSK/EDGE, QPSK TD-SCDMA and 10 MHz QPSK TD-LTE signals.
A novel ultra-wideband (UWB) bandpass filter with high selectivity and compact size is proposed in this letter. The major architecture of this filter is a coplanar waveguide (CPW)-microstrip-CPW transition from broadband balun mechanism. This structure has UWB bandpass characteristic and a transmission zero at its lower transition band. And some complementary split ring resonators (CSRR) are added in the ground of microstrip. A transmission zero located in upper transition band of filter is introduced by these CSRRs. Besides, the size of filter is only 0.25λg × 0.36λg (λg is the guided wavelength of 6.85 GHz). Finally, a filter prototype is fabricated and measured. The measured results show that its 3 dB passband covers 2.9 to 11 GHz. And two transmission zeros are located at 2.45 GHz and 11.45 GHz, which means the proposed filter presents high selectivity of 0.9 skirt factor.
This paper presents a novel leaky wave antenna (LWA) loaded by periodical open stubs and holes. The complex propagation constants of the first higher order mode of the periodically loaded microstrip, so-called the EH1 mode, are extracted by the field eigenvalue approach, leading to control the radiation characteristics by changing the loading conditions. By doubling the length of open stub, the operating frequency of the LWA can be shifted 8.9% toward to the lower frequency. The comparison of the dispersion curves between the loaded and conventional microstrips shows 20% width reduction on synthesizing the EH1 mode. Two 9 GHz and 10 GHz practical prototypes are designed based on the proposed methodology and fabricated by using the multilayer printed circuit board (PCB) technology. The measured return-losses of two LWA prototypes are lower than 10 dB. The measured antenna gains of two LWA are 5.37 dBi and 6.89 dBi. The maximum gains are 6.05 dBi and 7.43 dBi at 9.2 and 10.1 GHz. The beam scanning angles are 7 degrees and 4 degrees when the frequency is increased 0.2 GHz.
This paper proposes a novel multi-channel compressed structure to estimate directions of arrival (DOAs) of broadband signals based on the Nyquist folding structure. This paper firstly proposes a novel multi-channel receiving structure on a long-short baseline interferometer array and analyzes the feasibility of this structure applied in the DOAs estimation of broadband signals. Next, this paper proposes a special frequency estimation algorithm of the input signals under this structure. Finally, the DOAs of signals are estimated by using the long-short baseline interferometer algorithm. Computer simulations show that the proposed algorithm under the novel structure works well and this structure can estimate the DOAs of broadband signals stably when the signal-to-noise ratio (SNR) of the input signals is greater than 0 dB.
This paper presents a burst-mode clock and data recovery (CDR) circuit based on two symmetric quadrature phase VCO’s. The reduced loop locking time of less than 5 bits was achieved without any extra delay circuits which are added in conventional schemes for timing control. The proposed circuit is designed in 350 nm CMOS process and its feasibility has been proved successfully operating at 1.25 Gb/s.