In medical field, gaining access to blood vessels vitally important since it is the first step of many medical procedures. However, if vascular access is not established correctly, it causes complications. In this letter, we propose an algorithm that precisely segments blood vessels and automatically determines an injection point for injection robot systems using a monocular near-infrared vision system. The algorithm includes a Gaussian mixture model to determine the appropriate injection point for segmented blood vessels in a vision system and an ultrasound imaging system to estimate the depth of the blood vessel. Finally, we show the success rate of the proposed algorithm using phantom vessels.

This letter presents a high-linearity single-pole five-throw switch implemented in a 0.13-µm silicon-on-insulator (SOI) CMOS process. In order to improve the linearity of switch, the uniform voltage division across the stacked-FETs is obtained by the proposed structure, which employs a resistive biasing network as well as compensation technology of drain-to-source capacitance and DC balance resistor. The measured input 0.1dB compression point of the proposed switch is 42dBm. Insertion losses are 0.38dB and 0.5dB for TX and RX modes at 0.9GHz. The switch exhibits a second harmonic of -91dBc, and third harmonic power of -84dBc with a +28dBm input power at 0.9GHz.

In this letter, a high-efficiency 2.45GHz class-F voltage doubler rectifier is proposed for radio frequency energy harvesting (RFEH). In the proposed topology, two harmonic termination circuits are employed to shape the current waveform to half sine wave and voltage waveform to square wave by yielding short termination at even harmonics and open termination at odd harmonics. Compared with previous class-F voltage doubler rectifiers, the proposed rectifier achieves a higher RF-DC power conversion efficiency (PCE). To validate the proposed approach, a 2.45GHz voltage doubler rectifier has been designed and implemented. The measurement results show that the peak RF-DC PCE is 76% with a 15.6dBm input power range. In addition, the measured PCE is higher than 50% over the input power range from 2 to 18dBm.

A novel structure to design a fully integrated wideband 360° analog phase shifter (PS) from 2 to 6GHz is presented in this letter. This novel structure uses magnetically coupled all-pass networks (MCAPNs) cascaded with different center frequencies to construct a relatively flat broadband phase response. Furthermore, to solve the problem that MCAPN is hard to realize at the chip level when high frequencies, a tunable low-pass network (LPN) is introduced to compensate for the high-frequency band phase response. Unlike the existing methods, the new structure makes the bandwidth of PS more comprehensive, and the in-band flatness is better. For verification, a wideband monolithic microwave integrated circuit (MMIC) analog PS was designed and fabricated using a 2-µm gallium arsenide (GaAs) based heterojunction bipolar transistor (HBT) process. Measurement results show that the fabricated analog PS has a low average insertion loss of 6.0±0.56dB, low root mean square (rms) amplitude error of <0.9dB, and low rms phase error of <9° from 2-6GHz. The proposed analog PS has the most significant bandwidth compared with other reported passive phase shifters maintaining flat phase shift characteristics.

Wireless power transfer requires multilevel energy conversion for energy transfer, resulting in a bulky system. This paper proposes a direct AC-AC converter topology denoted as double half-bridge series-matrix converter and introduces a symmetric modulation method that eliminates the need for input voltage polarity detection. The converter circumvents DC conversion and operates at a unit power factor without the assistance of power factor correction. A 1kw prototype was constructed and the same control strategy was adopted, without considering the polarity or magnitude of the input voltage, verifying the accuracy and reliability of the proposed topology. The transmission efficiency was achieved at 91.43%.

In this letter, we propose a compact broadband and high-gain metasurface antenna (MSA) loaded with meander-line, which is made up of 3×3 square patches and two rows of meander-line. The meander-line is printed underneath the side radiating gap of the square patches, aiming to enforce the inter-element equivalent inductance for reducing the radiation aperture and increasing the BW of the MSA, simultaneously. A large bandwidth of 40% (|S₁₁|<-10dB) with the boresight peak gain of 9.2dBi is achieved, while the radiation aperture is only 0.46λ₀×0.46λ₀, which presents a good performance. The prototype of this MSA is manufactured and tested, the tested results correlated reasonably with the simulated ones.

In this paper, a design methodology of a novel ultra-wideband (UWB) Doherty power amplifier (DPA) monolithic microwave integrated circuit (MMIC) fabricated in a 0.25µm GaN-HEMT process is presented. To improve the saturated and 6-dB back-off efficiency of the DPA, an ultra-wideband enhanced load modulation technique is presented. A dual-frequency output impedance transformer (OIT) of the peaking amplifier is proposed to extend the enhanced load-modulation bandwidth. For verification, an ultra-wideband high efficiency DPA working over 4.3-5.6GHz has been designed and fabricated. The measurement results show that the DPA exhibits a small-signal gain of 12.2-14.5dB, an output power of 39.5-41dBm, a 6-dB back-off power added efficiency (PAE) of 40.2%-47.4%, and a saturated PAE of 47%-54.6% over the entire band. The proposed DPA demonstrates the highest saturated and 6-dB back-off PAE among published broadband GaN MMIC DPAs operating in similar bandwidth.

Logic locking is an efficient defense against attacks to the intellectual property of integrated circuits. However, in recent years, boolean satisfaction based attack (SAT attack) and a structural based attack named Valkyrie were proposed. As far as we know, most of the locking methods failed to achieve security for both of them and keep an acceptable overhead. In this paper, we present a self-adaptive striped-function logic locking method named SFLL-AD, based on repeatedly modifying the structure of the encryption block to a form that: (1) permits splitting and dispersing the encryption block across the netlist to have resilience to Valkryie (2) and guarantees not losing SAT resilience. Experimental results of our mehtod confirm the security to both attacks and show a small overhead (about 10% on average).

We propose a new model for parametrically evaluating the routability of GRM FPGA. By studying GRM FPGA, we can evaluate two-level mux structure. The input of our model is architecture parameters, and output is the routability estimation. Our model first generates directed graphs, which are used to model the FPGA routing architecture, and then analyzes the directed graphs to obtain the routability estimate. We show that our model can correctly predict the trend of routability while costing less time.

A wide-frequency all-digital duty cycle corrector with self-adaptive configurable delay chain is proposed. The proposed circuit can detect the alterations of clock frequency and the variations of PVT, and utilizes self-adaptive feedback loop to ensure that the circuit can achieve duty cycle correction within a wide operating frequency range. The test chip is fabricated in 130nm CMOS process, the area occupies 0.016mm². The chip testing results indicate that the correction error is within 2% throughout the input duty cycle from 20% to 80% at the frequency from 260MHz to 1GHz.

The omnidirectional wireless power transmission (WPT) technology have higher degree of freedom and less limitation in direction and space than the traditional WPT technology. This paper proposes a novel three-dimensional transmitter for omnidirectional wireless power transmission technology research. First, the magnetic field intensity distribution generated when three Tx coils are fed with different current phases is evaluated and analyzed. Then, the circuit topology of the system was analyzed and the mutual inductance between the transmitter (Tx) and receiver (Rx) coils was derived. Finally, an omnidirectional WPT experimental system was set up to validate all theoretical analyses.

We present a sub-terahertz (THz) wireless link using photonics-based ultra-low phase noise transmitter and receiver. The maximum data rate achieved below hard-decision forward error correction (HD-FEC) threshold by using on-line signal processing was 240Gbit/s with 64 quadrature amplitude modulation (64QAM) at a single carrier frequency of 275GHz. We also demonstrate successful 20-m transmission at a data rate of over-200Gbit/s data rate. This is the highest single-channel performance ever reported with sub-THz wireless communications to the best of our knowledge.

The traditional complementary metal oxide semiconductor (CMOS) process technology is approaching its limits due to the continuous shrinking of current semiconductor processes, which has implications for all aspects including device size, performance, power consumption, etc. These aspects also create bottlenecks in traditional Von Neumann computing architecture. As a new type of device that integrates computing and storage functions, the memristor is thus one of the candidates for breaking the mold in the post-Moore era. Here, we study TaO_x-based memristors from a simulation point of view, which is one of the best-performing memristors available. Firstly, we combine the quantum point contact (QPC) model and thermal dissolution mechanism to build a compact Verilog-A model of the TaO_x memristor, which is in good agreement with the experimental characterization data of TaO_x devices. Then, we apply the compact model of TaO_x memristor to logic circuits, and construct a new XOR gate based on the principle of memristor ratio logic (MRL), which can be used to cascade multiple logic gates. Furthermore, we extend these simple logic gates to construct a 1-bit full adder. The results show that the circuit described in this work is much improved in terms of power consumption and integration density compared to conventional CMOS circuits.

This paper presents a DC-coupled, incremental ΔΣ analog-to-digital converter (ADC) based on two-step quantization for high-density implantable neural signal recording. To address the problem of electrode DC offset (EDO), a compensation circuit is proposed in this paper which can automatically cancel the EDO. Fabricated in a 180-nm CMOS process, the prototype ADC achieves a high input impedance, 20-mVpp linear input range, 60.3-dB signal-to-noise and distortion ratio (SNDR). Its core circuit has a power consumption of 16µW and an area of 0.0165mm². The refered-to-input (RTI) noise is 6µVrms (1-10kHz) and it can cancel the EDO up to ±90mV.